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Single Cycle CPU

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module ALU(aluin1, aluin2, aluctrl, aluout, alubranch);
input[31:0] aluin1, aluin2;
input[3:0] aluctrl;
output reg[31:0] aluout;
output alubranch;
reg overflow;
reg[63:0] temp;
reg[31:0] HI, LO; // HI, LO register for multiplication and division.
assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
initial begin
temp = 64'h0000000000000000;
HI = 32'h00000000;
LO = 32'h00000000;
end
always @(*) begin
overflow = 0;
case(aluctrl)
4'b0000: aluout = aluin1 & aluin2; // and
4'b0001: aluout = aluin1 | aluin2; // or
4'b0010: begin // add
aluout = aluin1 + aluin2;
overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
end
4'b0110: begin // sub
aluout = aluin1 - aluin2;
overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
end
4'b0111: begin // slt
aluout[31:1] = {31{1'b0}};
aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0;
end
4'b1000: begin // mult
temp = aluin1 * aluin2;
HI = temp[63:32];
LO = temp[31:0];
end
4'b1001: begin // div
HI = aluin1 % aluin2;
LO = aluin1 / aluin2;
end
4'b1010: aluout = HI; // mfhi
4'b1011: aluout = LO; // mflo
4'b1100: aluout = ~(aluin1 | aluin2); // nor
4'b1101: aluout = aluin1 ^ aluin2; // xor
default: aluout = 32'b0;
endcase
end
endmodule
module ALUControl(funct, aluop, aluctrl);
input[5:0] funct;
input[1:0] aluop;
output reg[3:0] aluctrl;
always @(*) begin
case(aluop)
2'b00: aluctrl = 4'b0010; // add
2'b01: aluctrl = 4'b0110; // sub
2'b10: case(funct) // R type instruction
6'b100000: aluctrl = 4'b0010; // add
// 6'b100001: aluctrl = 4'b0010; // addu
6'b100010: aluctrl = 4'b0110; // sub
// 6'b100011: aluctrl = 4'b0110; // subu
6'b100100: aluctrl = 4'b0000; // and
6'b100101: aluctrl = 4'b0001; // or
6'b100110: aluctrl = 4'b1101; // xor
6'b011000: aluctrl = 4'b1000; // mult
// 6'b011001: aluctrl = 4'b1000; // multu
6'b011010: aluctrl = 4'b1001; // div
// 6'b011011: aluctrl = 4'b1001; // divu
6'b101010: aluctrl = 4'b0111; // slt
// 6'b101011: aluctrl = 4'b0111; // sltu
6'b010000: aluctrl = 4'b1010; // mfhi
6'b010010: aluctrl = 4'b1011; // mflo
default: aluctrl = 4'b1111;
endcase
default: aluctrl = 4'b1111;
endcase
end
endmodule
module Adder(adderinput1, adderinput2, adderoutput);
input[31:0] adderinput1, adderinput2;
output[31:0] adderoutput;
assign adderoutput = adderinput1 + adderinput2;
endmodule
module Control(opcode, regdst, regwrite, alusrc, aluop, memread, memwrite, memtoreg, branch, jump);
input[5:0] opcode;
output reg regdst, jump, branch, memread, memtoreg, memwrite, alusrc, regwrite;
output reg[1:0] aluop;
always @(*) begin
case(opcode)
6'b000000: begin // R type instruction
regdst = 1'b1;
regwrite = 1'b1;
alusrc = 1'b0;
aluop = 2'b10;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
end
6'b001000: begin // addi
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
end
6'b001001: begin // addiu
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
end
6'b000100: begin // beq
// regdst = 1'bx; // don't care
regwrite = 1'b0;
alusrc = 1'b0;
aluop = 2'b01;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b1;
jump = 1'b0;
end
6'b000010: begin // jump
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
// aluop = 2'bxx;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
end
6'b100011: begin // lw
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b1;
memwrite = 1'b0;
memtoreg = 1'b1;
branch = 1'b0;
jump = 1'b0;
end
6'b101011: begin // sw
regdst = 1'b0;
regwrite = 1'b0;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b1;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
end
default: begin
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
// branch = 1'bx;
// jump = 1'bx;
end
endcase
end
endmodule
module DataMemory(address, writedata, memread, memwrite, readdata);
input[31:0] address, writedata;
input memread, memwrite;
output[31:0] readdata;
reg[31:0] mem[255:0];
assign readdata = memread ? mem[address/4] : writedata;
always @(*) begin
if(memwrite==1'b1) begin
mem[address/4] = writedata;
end
end
endmodule
module InstructionMemory(address, instruction);
input[31:0] address;
output reg[31:0] instruction;
reg[31:0] instr_mem[127:0];
initial begin
instr_mem[0] = 32'd0;
instr_mem[1] = 32'b00100100000010000000000011111111; // addi $0 $8 255
instr_mem[2] = 32'b00000001000010000100100000100000; // add $8 $8 $9
instr_mem[3] = 32'b00000001000000000101000000100000; // add $8 $0 $10
instr_mem[4] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
instr_mem[5] = 32'b00000001000010010000000000011000; // mult $8 $9
instr_mem[6] = 32'd0;
instr_mem[7] = 32'b00000000000000000110000000010000; // mfhi $12
instr_mem[8] = 32'b00000000000000000110100000010010; // mflo $13
instr_mem[9] = 32'b10101100000011010000000000111100; // sw $0 $13 60
instr_mem[10] = 32'd0;
instr_mem[11] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
instr_mem[12] = 32'b10001100000000010000000000111100; // lw $0 $1 60
instr_mem[13] = 32'd0;
end
always @ (*) begin
instruction = instr_mem[address/4];
end
endmodule
module InstructionMemory(address, instruction);
input[31:0] address;
output reg[31:0] instruction;
reg[31:0] instr_mem[127:0];
initial begin
instr_mem[0] = 32'd0;
instr_mem[1] = 32'b00100100000010000000000011111111; // addi $0 $8 255
instr_mem[2] = 32'b00000001000010000100100000100000; // add $8 $8 $9
instr_mem[3] = 32'b00000001000000000101000000100000; // add $8 $0 $10
instr_mem[4] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
instr_mem[5] = 32'b00000001000010010000000000011000; // mult $8 $9
instr_mem[6] = 32'd0;
instr_mem[7] = 32'b00000000000000000110000000010000; // mfhi $12
instr_mem[8] = 32'b00000000000000000110100000010010; // mflo $13
instr_mem[9] = 32'b10101100000011010000000000111100; // sw $0 $13 15
instr_mem[10] = 32'd0;
instr_mem[11] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
instr_mem[12] = 32'b10001100000000010000000000111100; // lw $0 $1 60
instr_mem[13] = 32'd0;
end
always @ (*) begin
instruction = instr_mem[address/4];
end
endmodule
D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module testbench
Top level modules:
testbench
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Adder
Top level modules:
Adder
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module SignExtend
Top level modules:
SignExtend
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ALUControl
Top level modules:
ALUControl
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ShiftLeft2
Top level modules:
ShiftLeft2
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module test
Top level modules:
test
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Control
Top level modules:
Control
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ALU
Top level modules:
ALU
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Mux32bit
-- Compiling module Mux5bit
Top level modules:
Mux32bit
Mux5bit
} {} {}} {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v}
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module DataMemory
Top level modules:
DataMemory
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Clock
Top level modules:
Clock
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Register
Top level modules:
Register
} {} {}}
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module Mux32bit(muxin1, muxin2, signal, muxout);
input[31:0] muxin1, muxin2;
input signal;
output reg[31:0] muxout;
always @(*) begin
case(signal)
1'b0: muxout = muxin1;
1'b1: muxout = muxin2;
endcase
end
endmodule
module Mux5bit(muxin1, muxin2, signal, muxout);
input[4:0] muxin1, muxin2;
input signal;
output reg[4:0] muxout;
always @(*) begin
case(signal)
1'b0: muxout = muxin1;
1'b1: muxout = muxin2;
endcase
end
endmodule
module Register(readin1, readin2, writein, writedata, regwrite, regout1, regout2);
input[4:0] readin1, readin2, writein;
input[31:0] writedata;
input regwrite;
output[31:0] regout1, regout2;
integer i;
reg[31:0] register[31:0];
assign regout1 = register[readin1];
assign regout2 = register[readin2];
initial begin
for(i=0; i<32; i=i+1) register[i] = 32'd0;
end
always @(*) begin
if(regwrite == 1'b1 && writein != 5'd0) begin
register[writein] = writedata;
end
end
endmodule
module ShiftLeft2(shiftinput, shiftoutput);
input[31:0] shiftinput;
output[31:0] shiftoutput;
assign shiftoutput = {shiftinput[29:0], 2'b00};
endmodule
module SignExtend(signedinput, signedoutput);
input[15:0] signedinput;
output[31:0] signedoutput;
assign signedoutput = {{16{signedinput[15]}},signedinput};
endmodule
module Clock(clk);
output reg clk;
initial clk = 0;
always #50 clk = ~clk;
endmodule
module test;
reg[31:0] in1, in2;
reg[3:0] ctrl;
wire[31:0] out;
wire a;
ALU alu(in1, in2, ctrl, out, a);
initial begin
in1 = 32'd128;
in2 = 32'd982;
ctrl = 4'b1000;
#100;
in1 = 32'd123;
in2 = 32'd246;
ctrl = 4'b0010;
#100;
ctrl = 4'b1010;
#100;
ctrl = 4'b1011;
#100;
end
/*
wire clk;
Clock clock(clk);
*/
/*
reg[31:0] address, wdata;
reg mr, mw;
wire[31:0] rdata;
DataMemory damem(address, wdata, mr, mw, rdata);
initial begin
address = 32'd0;
wdata = 32'd127;
mr = 1'b0;
mw = 1'b1;
#100;
address = 32'd48;
wdata = 32'd255;
mr = 1'b0;
mw = 1'b1;
#100;
address = 32'd48;
wdata = 32'd255;
mr = 1'b1;
mw = 1'b0;
#100;
address = 32'd48;
wdata = 32'd4;
mr = 1'b0;
mw = 1'b1;
#100;
end
*/
/*
wire[31:0] regout1, regout2;
reg[4:0] ins1, ins2, ins3;
wire[31:0] aluresult;
reg[3:0] aluctrl;
reg rwrite;
reg[31:0] aluin2;
Register Regi(ins1, ins2, ins3, aluresult, rwrite, regout1, regout2);
ALU alu(regout1, aluin2, aluctrl, aluresult);
initial begin
rwrite = 1;
ins1 = 5'd0;
ins2 = 5'd29;
ins3 = 5'd7;
aluin2 = 32'h7fffffff;
aluctrl = 4'b0010;
#100;
rwrite = 1;
ins1 = 5'd7;
ins2 = 5'd7;
ins3 = 5'd8;
aluctrl = 4'b0010;
#100;
rwrite = 0;
#100;
rwrite = 1;
ins1 = 5'd0;
ins2 = 5'd29;
ins3 = 5'd7;
aluin2 = 32'h7fffffff;
aluctrl = 4'b0010;
#100;
rwrite = 1;
ins1 = 5'd7;
ins2 = 5'd7;
ins3 = 5'd8;
aluctrl = 4'b0010;
#100;
end
*/
/*
reg[31:0] input1, input2;
reg[3:0] ctrl;
wire[31:0] output1;
wire zero;
ALU testalu(input1, input2, ctrl, output1, zero);
initial begin
input1 <= 32'h0000000f;
input2 <= 32'h000000f0;
ctrl <= 4'h0; // add
#100;
ctrl <= 4'h1; // or
#100;
ctrl <= 4'h2; // add
#100;
ctrl <= 4'h6; // sub
#100;
ctrl <= 4'h7; // slt
#100;
ctrl <= 4'hc; // nor
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
end
*/
/*
reg[31:0] input1;
wire[31:0] output1;
InstructionMemory im(input1, output1);
initial
begin
input1 = {{28{1'b0}}, 4'b0000};
#100;
input1 = {{28{1'b0}}, 4'b1100};
#100;
input1 = {{28{1'b0}}, 4'b1000};
#100;
input1 = {{28{1'b0}}, 4'b0100};
#100;
input1 = {{28{1'b0}}, 4'b0000};
#100;
end
*/
/*
reg[7:0] input1;
wire[7:0] output1;
Adder adder1(input1, 8'b00000001, output1);
initial
begin
input1 = 8'b00001111;
#100;
input1 = 8'b00001000;
#100;
input1 = 8'b00000000;
#100;
input1 = 8'b11111111;
#100;
end
*/
endmodule
module testbench;
/*
wire clk; // clock
reg[31:0] PC; // program counter
reg[31:0] instr_address;
wire[31:0] addPC4, addPCbranch, tempPC1, nextPC;
wire[31:0] instr; // loaded instruction.
wire[4:0] reg_writereg1; // register number for the write data.
wire[31:0] reg_writedata; // data that will be written in the register.
wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
wire[31:0] alu_input2; // input data of ALU.
wire[31:0] alu_result; // result data of ALU.
wire alu_branch; // indicator for branch operation.
wire[31:0] mem_readdata; // data from the requested address.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump;
wire[1:0] ctrl_aluop; // control signals.
wire[3:0] aluctrl; // alu control signal.
wire[31:0] extend_output;
wire[31:0] shiftBranch_output;
wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(instr_address, instr);
Register register(instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
ALU alu(reg_readdata1, alu_input2, aluctrl, alu_result, alu_branch);
DataMemory datamem(alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
Control ctrl(instr[31:26], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
ALUControl ALUctrl(instr[5:0], ctrl_aluop, aluctrl);
Mux5bit mux_writereg(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
Mux32bit mux_alu(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
Mux32bit mux_writedata(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC1);
Mux32bit mux_jump(tempPC1, {addPC4[31:28], shiftJump_output[27:0]}, ctrl_jump, nextPC);
SignExtend extend(instr[15:0], extend_output);
Adder add_pc4(PC, 32'h00000004, addPC4);
Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
initial begin
PC = 32'h00000000;
end
always @(posedge clk) begin
case(nextPC[31]) // if nextPC is available, PC = nextPC.
1'b0: PC = nextPC;
1'b1: PC = nextPC;
endcase
instr_address = PC;
end
*/
wire clk; // clock
reg[31:0] PC, nextPC; // program counter
// Instruction Memory (IM)
reg[31:0] address; // instruction address. input of IM.
wire[31:0] instr; // loaded instruction. output of IM
// Register
reg[4:0] reg_readreg1, reg_readreg2; // register numbers of the read data. input of register.
reg[4:0] reg_writereg1; // register number for the write data. input of register.
reg[31:0] reg_writedata; // data that will be written in the register. input of register.
reg reg_sig_regwrite; // regwrite control signal. input of register
wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. outputs of register.
// ALU
reg[31:0] alu_input1, alu_input2; // input data of ALU. inputs of ALU.
reg[3:0] alu_control; // ALU control signal. input of ALU.
wire[31:0] alu_result; // result data of ALU. output of ALU.
wire alu_branch; // indicator for branch operation. output of ALU.
//Data Memory (DM)
reg[31:0] mem_addr; // address of the read data. input of DM.
reg[31:0] mem_writedata; // data that will be written in the memory. input of DM.
reg mem_memread, mem_memwrite; // control signals for DM. input of DM.
wire[31:0] mem_readdata; // data from the requested address. output of DM.
// Control Unit
reg[5:0] ctrl_opcode; // opcode of the instruction. input of control unit.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread; // ??
wire ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump; // ??? control signals outputs of control unit.
wire[1:0] ctrl_aluop; // ??
// ALU Control Unit
reg[5:0] aluctrl_funct; // function code of the R type instructions. input of ALU control unit.
reg[1:0] aluctrl_aluop; // aluop signal. input of ALU control unit.
wire[3:0] aluctrl_sig; // alu control signal. output of ALU control unit.
// Multiplexer (Mux)
// mux_writereg Mux for Write Register.
reg[4:0] mux_writereg_input1, mux_writereg_input2;
reg mux_writereg_signal;
wire[4:0] mux_writereg_output;
// mux_alu Mux for ALU input 2.
reg[31:0] mux_alu_input1, mux_alu_input2;
reg mux_alu_signal;
wire[31:0] mux_alu_output;
// mux_writedata Mux for Write Data of Register.
reg[31:0] mux_writedata_input1, mux_writedata_input2;
reg mux_writedata_signal;
wire[31:0] mux_writedata_output;
// mux_branch Mux for Branch
reg[31:0] mux_branch_input1, mux_branch_input2;
reg mux_branch_signal;
wire[31:0] mux_branch_output;
// mux_jump Mux for Jump
reg[31:0] mux_jump_input1, mux_jump_input2;
reg mux_jump_signal;
wire[31:0] mux_jump_output;
// Sign Extend
reg[15:0] extend_input;
wire[31:0] extend_output;
// Adder
// add_pc4
reg[31:0] add_pc4_input; // input2 is 4.
wire[31:0] add_pc4_output;
// add_branch
reg[31:0] add_branch_input1, add_branch_input2;
wire[31:0] add_branch_output;
// Shift Left 2
// shiftBranch ShiftLeft2 which is used for Branch instructions.
reg[31:0] shiftBranch_input;
wire[31:0] shiftBranch_output;
// shiftJump ShiftLeft2 which is used for Jump instructions.
reg[31:0] shiftJump_input;
wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(address, instr);
Register register(reg_readreg1, reg_readreg2, reg_writereg1, reg_writedata, reg_sig_regwrite, reg_readdata1, reg_readdata2);
ALU alu(alu_input1, alu_input2, alu_control, alu_result, alu_branch);
DataMemory datamem(mem_addr, mem_writedata, mem_memread, mem_memwrite, mem_readdata);
Control ctrl(ctrl_opcode, ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
ALUControl aluctrl(aluctrl_funct, aluctrl_aluop, aluctrl_sig);
Mux5bit mux_writereg(mux_writereg_input1, mux_writereg_input2, mux_writereg_signal, mux_writereg_output);
Mux32bit mux_alu(mux_alu_input1, mux_alu_input2, mux_alu_signal, mux_alu_output);
Mux32bit mux_writedata(mux_writedata_input1, mux_writedata_input2, mux_writedata_signal, mux_writedata_output);
Mux32bit mux_branch(mux_branch_input1, mux_branch_input2, mux_branch_signal, mux_branch_output);
Mux32bit mux_jump(mux_jump_input1, mux_jump_input2, mux_jump_signal, mux_jump_output);
SignExtend extend(extend_input, extend_output);
Adder add_pc4(add_pc4_input, 32'h00000004, add_pc4_output);
Adder add_branch(add_branch_input1, add_branch_input2, add_branch_output);
ShiftLeft2 shiftBranch(shiftBranch_input, shiftBranch_output);
ShiftLeft2 shiftJump(shiftJump_input, shiftJump_output);
initial begin
PC = 32'h00000000;
nextPC = 32'h00000000;
end
always @(posedge clk) begin
// IF
case(nextPC[0])
1'b0: PC = nextPC;
1'b1: PC = nextPC;
endcase
#1;
address = PC;
add_pc4_input = PC;
#1;
// ID
ctrl_opcode <= instr[31:26];
reg_readreg1 <= instr[25:21];
reg_readreg2 <= instr[20:16];
mux_writereg_input1 <= instr[20:16];
mux_writereg_input2 <= instr[15:11];
extend_input <= instr[15:0];
aluctrl_funct <= instr[5:0];
shiftJump_input <= {6'b000000, instr[25:0]};
#1;
mux_writereg_signal <= ctrl_regdst;
aluctrl_aluop <= ctrl_aluop;
// EX
mux_alu_input1 <= reg_readdata2;
mux_alu_input2 <= extend_output;
mux_alu_signal <= ctrl_alusrc;
shiftBranch_input <= extend_output;
#1;
alu_input1 <= reg_readdata1;
alu_input2 <= mux_alu_output;
alu_control <= aluctrl_sig;
add_branch_input1 <= add_pc4_output;
add_branch_input2 <= shiftBranch_output;
#1;
mux_branch_input1 <= add_pc4_output;
mux_branch_input2 <= add_branch_output;
mux_branch_signal <= ctrl_branch & alu_branch;
#1;
// MEM
mux_jump_input1 <= mux_branch_output;
mux_jump_input2 <= {add_pc4_output[31:28], shiftJump_output[27:0]};
mux_jump_signal <= ctrl_jump;
mem_addr <= alu_result;
mem_writedata <= reg_readdata2;
mem_memread <= ctrl_memread;
mem_memwrite <= ctrl_memwrite;
#1;
// WB
mux_writedata_input1 <= alu_result;
mux_writedata_input2 <= mem_readdata;
mux_writedata_signal <= ctrl_memtoreg;
#1;
reg_sig_regwrite <= ctrl_regwrite;
reg_writereg1 <= mux_writereg_output;
reg_writedata <= mux_writedata_output;
#1;
nextPC <= mux_jump_output;
end
endmodule
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