Control.v
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module Control(opcode, regdst, regwrite, alusrc, aluop, memread, memwrite, memtoreg, branch, jump);
input[5:0] opcode;
output reg regdst, jump, branch, memread, memtoreg, memwrite, alusrc, regwrite;
output reg[1:0] aluop;
always @(*) begin
case(opcode)
6'b000000: begin // R type instruction
regdst = 1'b1;
regwrite = 1'b1;
alusrc = 1'b0;
aluop = 2'b10;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
end
6'b001000: begin // addi
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
end
6'b001001: begin // addiu
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
end
6'b000100: begin // beq
// regdst = 1'bx; // don't care
regwrite = 1'b0;
alusrc = 1'b0;
aluop = 2'b01;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b1;
jump = 1'b0;
end
6'b000010: begin // jump
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
// aluop = 2'bxx;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
end
6'b100011: begin // lw
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b1;
memwrite = 1'b0;
memtoreg = 1'b1;
branch = 1'b0;
jump = 1'b0;
end
6'b101011: begin // sw
regdst = 1'b0;
regwrite = 1'b0;
alusrc = 1'b1;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b1;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
end
default: begin
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluop = 2'b00;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
// branch = 1'bx;
// jump = 1'bx;
end
endcase
end
endmodule