test.v
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module test;
reg[31:0] in1, in2;
reg[3:0] ctrl;
wire[31:0] out;
wire a;
ALU alu(in1, in2, ctrl, out, a);
initial begin
in1 = 32'd128;
in2 = 32'd982;
ctrl = 4'b1000;
#100;
in1 = 32'd123;
in2 = 32'd246;
ctrl = 4'b0010;
#100;
ctrl = 4'b1010;
#100;
ctrl = 4'b1011;
#100;
end
/*
wire clk;
Clock clock(clk);
*/
/*
reg[31:0] address, wdata;
reg mr, mw;
wire[31:0] rdata;
DataMemory damem(address, wdata, mr, mw, rdata);
initial begin
address = 32'd0;
wdata = 32'd127;
mr = 1'b0;
mw = 1'b1;
#100;
address = 32'd48;
wdata = 32'd255;
mr = 1'b0;
mw = 1'b1;
#100;
address = 32'd48;
wdata = 32'd255;
mr = 1'b1;
mw = 1'b0;
#100;
address = 32'd48;
wdata = 32'd4;
mr = 1'b0;
mw = 1'b1;
#100;
end
*/
/*
wire[31:0] regout1, regout2;
reg[4:0] ins1, ins2, ins3;
wire[31:0] aluresult;
reg[3:0] aluctrl;
reg rwrite;
reg[31:0] aluin2;
Register Regi(ins1, ins2, ins3, aluresult, rwrite, regout1, regout2);
ALU alu(regout1, aluin2, aluctrl, aluresult);
initial begin
rwrite = 1;
ins1 = 5'd0;
ins2 = 5'd29;
ins3 = 5'd7;
aluin2 = 32'h7fffffff;
aluctrl = 4'b0010;
#100;
rwrite = 1;
ins1 = 5'd7;
ins2 = 5'd7;
ins3 = 5'd8;
aluctrl = 4'b0010;
#100;
rwrite = 0;
#100;
rwrite = 1;
ins1 = 5'd0;
ins2 = 5'd29;
ins3 = 5'd7;
aluin2 = 32'h7fffffff;
aluctrl = 4'b0010;
#100;
rwrite = 1;
ins1 = 5'd7;
ins2 = 5'd7;
ins3 = 5'd8;
aluctrl = 4'b0010;
#100;
end
*/
/*
reg[31:0] input1, input2;
reg[3:0] ctrl;
wire[31:0] output1;
wire zero;
ALU testalu(input1, input2, ctrl, output1, zero);
initial begin
input1 <= 32'h0000000f;
input2 <= 32'h000000f0;
ctrl <= 4'h0; // add
#100;
ctrl <= 4'h1; // or
#100;
ctrl <= 4'h2; // add
#100;
ctrl <= 4'h6; // sub
#100;
ctrl <= 4'h7; // slt
#100;
ctrl <= 4'hc; // nor
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
input1 <= 32'h000000f0;
input2 <= 32'h0000000f;
ctrl <= 4'h6; // sub
#100;
end
*/
/*
reg[31:0] input1;
wire[31:0] output1;
InstructionMemory im(input1, output1);
initial
begin
input1 = {{28{1'b0}}, 4'b0000};
#100;
input1 = {{28{1'b0}}, 4'b1100};
#100;
input1 = {{28{1'b0}}, 4'b1000};
#100;
input1 = {{28{1'b0}}, 4'b0100};
#100;
input1 = {{28{1'b0}}, 4'b0000};
#100;
end
*/
/*
reg[7:0] input1;
wire[7:0] output1;
Adder adder1(input1, 8'b00000001, output1);
initial
begin
input1 = 8'b00001111;
#100;
input1 = 8'b00001000;
#100;
input1 = 8'b00000000;
#100;
input1 = 8'b11111111;
#100;
end
*/
endmodule