module Mux32bit(muxin1, muxin2, signal, muxout);

input[31:0] muxin1, muxin2;
input signal;
output reg[31:0] muxout;

always @(*) begin
case(signal)
	1'b0: muxout = muxin1;
	1'b1: muxout = muxin2;
endcase
end

endmodule

module Mux5bit(muxin1, muxin2, signal, muxout);

input[4:0] muxin1, muxin2;
input signal;
output reg[4:0] muxout;

always @(*) begin
case(signal)
	1'b0: muxout = muxin1;
	1'b1: muxout = muxin2;
endcase
end

endmodule