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1 -module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch);
2 -
3 -input clk;
4 -input[31:0] aluin1, aluin2;
5 -input[3:0] aluctrl;
6 -output reg[31:0] aluout;
7 -output alubranch;
8 -
9 -reg overflow;
10 -reg[63:0] temp;
11 -reg[31:0] HI, LO; // HI, LO register for multiplication and division.
12 -reg[31:0] HI, LO; // HI, LO register for multiplication and division.
13 -
14 -assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
15 -
16 -initial begin
17 - temp = 64'h0000000000000000;
18 - tempHI = 32'h00000000;
19 - tempLO = 32'h00000000;
20 - HI = 32'h00000000;
21 - LO = 32'h00000000;
22 -end
23 -
24 -always @(*) begin
25 -overflow = 0;
26 -case(aluctrl)
27 - 4'b0000: aluout <= aluin1 & aluin2; // and
28 - 4'b0001: aluout <= aluin1 | aluin2; // or
29 - 4'b0010: begin // add
30 - aluout = aluin1 + aluin2;
31 - overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
32 - end
33 - 4'b0110: begin // sub
34 - aluout = aluin1 - aluin2;
35 - overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
36 - end
37 -
38 - 4'b0111: begin // slt
39 - aluout[31:1] = {31{1'b0}};
40 - aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0;
41 - end
42 - 4'b1000: begin // mult
43 - temp = aluin1 * aluin2;
44 - tempHI <= temp[63:32];
45 - tempLO <= temp[31:0];
46 - end
47 - 4'b1001: begin // div
48 - tempHI <= aluin1 % aluin2;
49 - tempLO <= aluin1 / aluin2;
50 - end
51 - 4'b1010: aluout <= HI; // mfhi
52 - 4'b1011: aluout <= LO; // mflo
53 - 4'b1100: aluout <= ~(aluin1 | aluin2); // nor
54 - 4'b1101: aluout <= aluin1 ^ aluin2; // xor
55 - default: aluout <= 32'b0;
56 -endcase
57 -end
58 -
59 -always @(negedge clk) begin
60 - case(aluctrl)
61 - 4'b1000: begin // mult
62 - HI <= tempHI;
63 - LO <= tempLO;
64 - end
65 - 4'b1001: begin // div
66 - HI <= tempHI;
67 - LO <= tempLO;
68 - end
69 - endcase
70 - tempHI = 32'd0;
71 - tempLO = 32'd0;
72 -end
73 -
74 -endmodule
1 -module ALUControl(funct, aluop, aluctrl);
2 -
3 -input[5:0] funct;
4 -input[1:0] aluop;
5 -output reg[3:0] aluctrl;
6 -
7 -always @(*) begin
8 - case(aluop)
9 - 2'b00: aluctrl = 4'b0010; // add
10 - 2'b01: aluctrl = 4'b0110; // sub
11 - 2'b10: case(funct) // R type instruction
12 - 6'b100000: aluctrl = 4'b0010; // add
13 - // 6'b100001: aluctrl = 4'b0010; // addu
14 - 6'b100010: aluctrl = 4'b0110; // sub
15 - // 6'b100011: aluctrl = 4'b0110; // subu
16 - 6'b100100: aluctrl = 4'b0000; // and
17 - 6'b100101: aluctrl = 4'b0001; // or
18 - 6'b100110: aluctrl = 4'b1101; // xor
19 - 6'b011000: aluctrl = 4'b1000; // mult
20 - // 6'b011001: aluctrl = 4'b1000; // multu
21 - 6'b011010: aluctrl = 4'b1001; // div
22 - // 6'b011011: aluctrl = 4'b1001; // divu
23 - 6'b101010: aluctrl = 4'b0111; // slt
24 - // 6'b101011: aluctrl = 4'b0111; // sltu
25 - 6'b010000: aluctrl = 4'b1010; // mfhi
26 - 6'b010010: aluctrl = 4'b1011; // mflo
27 -
28 - default: aluctrl = 4'b1111;
29 - endcase
30 - default: aluctrl = 4'b1111;
31 - endcase
32 -end
33 -
34 -endmodule
1 -module Control(opcode, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
2 -
3 -input[5:0] opcode;
4 -input[5:0] funct;
5 -output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, branch, jump, jumpreg;
6 -output reg[3:0] aluctrl;
7 -
8 -always @(*) begin
9 - case(opcode)
10 - 6'b000000: begin // R type instruction
11 - regdst = 1'b1;
12 - regwrite = 1'b1;
13 - alusrc = 1'b0;
14 - memread = 1'b0;
15 - memwrite = 1'b0;
16 - memtoreg = 1'b0;
17 - branch = 1'b0;
18 - jump = 1'b0;
19 - jumpreg = 1'b0;
20 - case(funct)
21 - 6'b100000: aluctrl = 4'b0010; // add
22 - 6'b100001: aluctrl = 4'b0010; // addu
23 - 6'b100010: aluctrl = 4'b0110; // sub
24 - 6'b100011: aluctrl = 4'b0110; // subu
25 - 6'b100100: aluctrl = 4'b0000; // and
26 - 6'b100101: aluctrl = 4'b0001; // or
27 - 6'b100110: aluctrl = 4'b1101; // xor
28 - 6'b011000: aluctrl = 4'b1000; // mult
29 - 6'b011001: aluctrl = 4'b1000; // multu
30 - 6'b011010: aluctrl = 4'b1001; // div
31 - 6'b011011: aluctrl = 4'b1001; // divu
32 - 6'b101010: aluctrl = 4'b0111; // slt
33 - 6'b101011: aluctrl = 4'b0111; // sltu
34 - 6'b010000: aluctrl = 4'b1010; // mfhi
35 - 6'b010010: aluctrl = 4'b1011; // mflo
36 - 6'b001000: begin // jr
37 - // regdst = 1'bx;
38 - regwrite = 1'b0;
39 - // alusrc = 1'bx;
40 - aluctrl = 4'b1111;
41 - memread = 1'b0;
42 - memwrite = 1'b0;
43 - // memtoreg = 1'bx;
44 - branch = 1'b0;
45 - jump = 1'b0;
46 - jumpreg = 1'b1;
47 - end
48 - default: aluctrl = 4'b1111;
49 - endcase
50 - end
51 -
52 - 6'b001000: begin // addi instruction
53 - regdst = 1'b0;
54 - regwrite = 1'b1;
55 - alusrc = 1'b1;
56 - aluctrl = 4'b0010; // add
57 - memread = 1'b0;
58 - memwrite = 1'b0;
59 - memtoreg = 1'b0;
60 - branch = 1'b0;
61 - jump = 1'b0;
62 - jumpreg = 1'b0;
63 - end
64 -
65 - 6'b001001: begin // addiu instruction
66 - regdst = 1'b0;
67 - regwrite = 1'b1;
68 - alusrc = 1'b1;
69 - aluctrl = 4'b0010; // add
70 - memread = 1'b0;
71 - memwrite = 1'b0;
72 - memtoreg = 1'b0;
73 - branch = 1'b0;
74 - jump = 1'b0;
75 - jumpreg = 1'b0;
76 - end
77 -
78 - 6'b001100: begin // andi instruction
79 - regdst = 1'b0;
80 - regwrite = 1'b1;
81 - alusrc = 1'b1;
82 - aluctrl = 4'b0000; // and
83 - memread = 1'b0;
84 - memwrite = 1'b0;
85 - memtoreg = 1'b0;
86 - branch = 1'b0;
87 - jump = 1'b0;
88 - jumpreg = 1'b0;
89 - end
90 -
91 - 6'b000100: begin // beq instruction
92 - // regdst = 1'bx; // don't care
93 - regwrite = 1'b0;
94 - alusrc = 1'b0;
95 - aluctrl = 4'b0110; // sub
96 - memread = 1'b0;
97 - memwrite = 1'b0;
98 - // memtoreg = 1'bx;
99 - branch = 1'b1;
100 - jump = 1'b0;
101 - jumpreg = 1'b0;
102 - end
103 -
104 - 6'b000010: begin // jump instruction
105 - // regdst = 1'bx;
106 - regwrite = 1'b0;
107 - // alusrc = 1'bx;
108 - aluctrl = 4'b1111;
109 - memread = 1'b0;
110 - memwrite = 1'b0;
111 - // memtoreg = 1'bx;
112 - branch = 1'b0;
113 - jump = 1'b1;
114 - jumpreg = 1'b0;
115 - end
116 -
117 - 6'b100011: begin // lw instruction
118 - regdst = 1'b0;
119 - regwrite = 1'b1;
120 - alusrc = 1'b1;
121 - aluctrl = 4'b0010; // add
122 - memread = 1'b1;
123 - memwrite = 1'b0;
124 - memtoreg = 1'b1;
125 - branch = 1'b0;
126 - jump = 1'b0;
127 - jumpreg = 1'b0;
128 - end
129 -
130 - 6'b101011: begin // sw instruction
131 - regdst = 1'b0;
132 - regwrite = 1'b0;
133 - alusrc = 1'b1;
134 - aluctrl = 4'b0010; // add
135 - memread = 1'b0;
136 - memwrite = 1'b1;
137 - // memtoreg = 1'bx;
138 - branch = 1'b0;
139 - jump = 1'b0;
140 - jumpreg = 1'b0;
141 - end
142 -
143 - default: begin // unknown instruction
144 - // regdst = 1'bx;
145 - regwrite = 1'b0;
146 - // alusrc = 1'bx;
147 - aluctrl = 4'b1111;
148 - memread = 1'b0;
149 - memwrite = 1'b0;
150 - // memtoreg = 1'bx;
151 - branch = 1'b0;
152 - jump = 1'b0;
153 - jumpreg = 1'b0;
154 - end
155 - endcase
156 -end
157 -
158 -endmodule
1 -module DataMemory(clk, address, writedata, memread, memwrite, readdata);
2 -
3 -input clk;
4 -input[31:0] address, writedata;
5 -input memread, memwrite;
6 -output[31:0] readdata;
7 -
8 -reg[31:0] mem[255:0];
9 -
10 -assign readdata = memread ? mem[address/4] : writedata;
11 -
12 -always @(negedge clk) begin
13 - if(memwrite==1'b1) begin
14 - mem[address/4] = writedata;
15 - end
16 -end
17 -
18 -endmodule
1 -module InstructionMemory(address, instruction);
2 -
3 -input[31:0] address;
4 -output reg[31:0] instruction;
5 -
6 -reg[31:0] instr_mem[127:0];
7 -
8 -initial begin
9 -instr_mem[0] = 32'd0;
10 -instr_mem[1] = 32'b00100100000010000000000011111111; // addi $0 $8 255
11 -instr_mem[2] = 32'b00000001000010000100100000100000; // add $8 $8 $9
12 -instr_mem[3] = 32'b00000001000000000101000000100000; // add $8 $0 $10
13 -instr_mem[4] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
14 -instr_mem[5] = 32'b00000001000010010000000000011000; // mult $8 $9
15 -instr_mem[6] = 32'd0;
16 -instr_mem[7] = 32'b00000000000000000110000000010000; // mfhi $12
17 -instr_mem[8] = 32'b00000000000000000110100000010010; // mflo $13
18 -instr_mem[9] = 32'b10101100000011010000000000111100; // sw $0 $13 60
19 -instr_mem[10] = 32'd0;
20 -instr_mem[11] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
21 -instr_mem[12] = 32'b10001100000000010000000000111100; // lw $0 $1 60
22 -instr_mem[13] = 32'd0;
23 -
24 -end
25 -
26 -always @ (*) begin
27 - instruction = instr_mem[address/4];
28 -end
29 -
30 -endmodule
1 -{D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} 1 +D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
2 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module DataMemory
4 -
5 -Top level modules:
6 - DataMemory
7 -
8 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 -- Compiling module ShiftLeft2 3 -- Compiling module ShiftLeft2
11 4
...@@ -19,6 +12,20 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -19,6 +12,20 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
19 Top level modules: 12 Top level modules:
20 InstructionMemory 13 InstructionMemory
21 14
15 +} {} {}} {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v}
16 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
17 +-- Compiling module DataMemory
18 +
19 +Top level modules:
20 + DataMemory
21 +
22 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
23 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
24 +-- Compiling module testbench
25 +
26 +Top level modules:
27 + testbench
28 +
22 } {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v 29 } {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
23 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 30 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
24 -- Compiling module Clock 31 -- Compiling module Clock
...@@ -33,12 +40,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -33,12 +40,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
33 Top level modules: 40 Top level modules:
34 Adder 41 Adder
35 42
36 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v 43 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
37 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 44 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
38 --- Compiling module testbench 45 +-- Compiling module SignExtend
39 46
40 Top level modules: 47 Top level modules:
41 - testbench 48 + SignExtend
42 49
43 } {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v 50 } {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
44 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 51 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -54,13 +61,6 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -54,13 +61,6 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
54 Top level modules: 61 Top level modules:
55 Control 62 Control
56 63
57 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
58 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
59 --- Compiling module SignExtend
60 -
61 -Top level modules:
62 - SignExtend
63 -
64 } {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v 64 } {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
65 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 65 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
66 -- Compiling module ALU 66 -- Compiling module ALU
......
1 -module Mux32bit(muxin1, muxin2, signal, muxout);
2 -
3 -input[31:0] muxin1, muxin2;
4 -input signal;
5 -output reg[31:0] muxout;
6 -
7 -always @(*) begin
8 -case(signal)
9 - 1'b0: muxout = muxin1;
10 - 1'b1: muxout = muxin2;
11 -endcase
12 -end
13 -
14 -endmodule
15 -
16 -module Mux5bit(muxin1, muxin2, signal, muxout);
17 -
18 -input[4:0] muxin1, muxin2;
19 -input signal;
20 -output reg[4:0] muxout;
21 -
22 -always @(*) begin
23 -case(signal)
24 - 1'b0: muxout = muxin1;
25 - 1'b1: muxout = muxin2;
26 -endcase
27 -end
28 -
29 -endmodule
30 -
31 -module Mux32bit4x1(muxin1, muxin2, muxin3, signal, muxout);
32 -
33 -input[31:0] muxin1, muxin2, muxin3;
34 -input[1:0] signal;
35 -output reg[31:0] muxout;
36 -
37 -always @(*) begin
38 -case(signal)
39 - 2'b00: muxout = muxin1;
40 - 2'b01: muxout = muxin2;
41 - 2'b11: muxout = muxin3;
42 -endcase
43 -end
44 -
45 -endmodule
1 -module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
2 -
3 -input clk;
4 -input[4:0] readin1, readin2, writein;
5 -input[31:0] writedata;
6 -input regwrite;
7 -output[31:0] regout1, regout2;
8 -
9 -integer i;
10 -reg[31:0] register[31:0];
11 -
12 -assign regout1 = register[readin1];
13 -assign regout2 = register[readin2];
14 -
15 -initial begin
16 - for(i=0; i<32; i=i+1) register[i] = 32'd0;
17 -end
18 -
19 -always @(*) begin
20 - if(regwrite == 1'b1 && writein != 5'd0) begin
21 - register[writein] = writedata;
22 - end
23 -end
24 -
25 -endmodule
1 -module testbench;
2 -
3 -wire clk; // clock
4 -reg[31:0] PC; // program counter
5 -reg[31:0] instr_address;
6 -wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
7 -
8 -wire[31:0] instr; // loaded instruction.
9 -
10 -wire[4:0] reg_writereg1; // register number for the write data.
11 -wire[31:0] reg_writedata; // data that will be written in the register.
12 -wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
13 -
14 -wire[31:0] alu_input2; // input data of ALU.
15 -wire[31:0] alu_result; // result data of ALU.
16 -wire alu_branch; // indicator for branch operation.
17 -
18 -wire[31:0] mem_readdata; // data from the requested address.
19 -
20 -wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg;
21 -wire[3:0] ctrl_aluctrl; // control signals.
22 -
23 -wire[31:0] extend_output;
24 -
25 -wire[31:0] shiftBranch_output;
26 -wire[31:0] shiftJump_output;
27 -
28 -Clock clock(clk);
29 -InstructionMemory instrmem(instr_address, instr);
30 -Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
31 -ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
32 -DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
33 -Control ctrl(instr[31:26], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
34 -Mux5bit mux_writereg(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
35 -Mux32bit mux_alu(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
36 -Mux32bit mux_writedata(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
37 -Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch);
38 -Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
39 -Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
40 -SignExtend extend(instr[15:0], extend_output);
41 -Adder add_pc4(PC, 32'h00000004, addPC4);
42 -Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
43 -ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
44 -ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
45 -
46 -initial begin
47 - PC = 32'h00000000;
48 -end
49 -
50 -always @(posedge clk) begin
51 - case(nextPC[31]) // if nextPC is available, PC = nextPC.
52 - 1'b0: PC = nextPC;
53 - 1'b1: PC = nextPC;
54 - endcase
55 -
56 - instr_address = PC;
57 -end
58 -
59 -/*
60 -wire clk; // clock
61 -reg[31:0] PC, nextPC; // program counter
62 -
63 -// Instruction Memory (IM)
64 -reg[31:0] address; // instruction address. input of IM.
65 -wire[31:0] instr; // loaded instruction. output of IM
66 -
67 -// Register
68 -reg[4:0] reg_readreg1, reg_readreg2; // register numbers of the read data. input of register.
69 -reg[4:0] reg_writereg1; // register number for the write data. input of register.
70 -reg[31:0] reg_writedata; // data that will be written in the register. input of register.
71 -reg reg_sig_regwrite; // regwrite control signal. input of register
72 -wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. outputs of register.
73 -
74 -// ALU
75 -reg[31:0] alu_input1, alu_input2; // input data of ALU. inputs of ALU.
76 -reg[3:0] alu_control; // ALU control signal. input of ALU.
77 -wire[31:0] alu_result; // result data of ALU. output of ALU.
78 -wire alu_branch; // indicator for branch operation. output of ALU.
79 -
80 -//Data Memory (DM)
81 -reg[31:0] mem_addr; // address of the read data. input of DM.
82 -reg[31:0] mem_writedata; // data that will be written in the memory. input of DM.
83 -reg mem_memread, mem_memwrite; // control signals for DM. input of DM.
84 -wire[31:0] mem_readdata; // data from the requested address. output of DM.
85 -
86 -// Control Unit
87 -reg[5:0] ctrl_opcode; // opcode of the instruction. input of control unit.
88 -wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread; // ??
89 -wire ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump; // ??? control signals outputs of control unit.
90 -wire[1:0] ctrl_aluop; // ??
91 -
92 -// ALU Control Unit
93 -reg[5:0] aluctrl_funct; // function code of the R type instructions. input of ALU control unit.
94 -reg[1:0] aluctrl_aluop; // aluop signal. input of ALU control unit.
95 -wire[3:0] aluctrl_sig; // alu control signal. output of ALU control unit.
96 -
97 -// Multiplexer (Mux)
98 - // mux_writereg Mux for Write Register.
99 -reg[4:0] mux_writereg_input1, mux_writereg_input2;
100 -reg mux_writereg_signal;
101 -wire[4:0] mux_writereg_output;
102 - // mux_alu Mux for ALU input 2.
103 -reg[31:0] mux_alu_input1, mux_alu_input2;
104 -reg mux_alu_signal;
105 -wire[31:0] mux_alu_output;
106 - // mux_writedata Mux for Write Data of Register.
107 -reg[31:0] mux_writedata_input1, mux_writedata_input2;
108 -reg mux_writedata_signal;
109 -wire[31:0] mux_writedata_output;
110 - // mux_branch Mux for Branch
111 -reg[31:0] mux_branch_input1, mux_branch_input2;
112 -reg mux_branch_signal;
113 -wire[31:0] mux_branch_output;
114 - // mux_jump Mux for Jump
115 -reg[31:0] mux_jump_input1, mux_jump_input2;
116 -reg mux_jump_signal;
117 -wire[31:0] mux_jump_output;
118 -
119 -// Sign Extend
120 -reg[15:0] extend_input;
121 -wire[31:0] extend_output;
122 -
123 -// Adder
124 - // add_pc4
125 -reg[31:0] add_pc4_input; // input2 is 4.
126 -wire[31:0] add_pc4_output;
127 - // add_branch
128 -reg[31:0] add_branch_input1, add_branch_input2;
129 -wire[31:0] add_branch_output;
130 -
131 -// Shift Left 2
132 - // shiftBranch ShiftLeft2 which is used for Branch instructions.
133 -reg[31:0] shiftBranch_input;
134 -wire[31:0] shiftBranch_output;
135 - // shiftJump ShiftLeft2 which is used for Jump instructions.
136 -reg[31:0] shiftJump_input;
137 -wire[31:0] shiftJump_output;
138 -
139 -
140 -Clock clock(clk);
141 -InstructionMemory instrmem(address, instr);
142 -Register register(reg_readreg1, reg_readreg2, reg_writereg1, reg_writedata, reg_sig_regwrite, reg_readdata1, reg_readdata2);
143 -ALU alu(alu_input1, alu_input2, alu_control, alu_result, alu_branch);
144 -DataMemory datamem(mem_addr, mem_writedata, mem_memread, mem_memwrite, mem_readdata);
145 -Control ctrl(ctrl_opcode, ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
146 -ALUControl aluctrl(aluctrl_funct, aluctrl_aluop, aluctrl_sig);
147 -Mux5bit mux_writereg(mux_writereg_input1, mux_writereg_input2, mux_writereg_signal, mux_writereg_output);
148 -Mux32bit mux_alu(mux_alu_input1, mux_alu_input2, mux_alu_signal, mux_alu_output);
149 -Mux32bit mux_writedata(mux_writedata_input1, mux_writedata_input2, mux_writedata_signal, mux_writedata_output);
150 -Mux32bit mux_branch(mux_branch_input1, mux_branch_input2, mux_branch_signal, mux_branch_output);
151 -Mux32bit mux_jump(mux_jump_input1, mux_jump_input2, mux_jump_signal, mux_jump_output);
152 -SignExtend extend(extend_input, extend_output);
153 -Adder add_pc4(add_pc4_input, 32'h00000004, add_pc4_output);
154 -Adder add_branch(add_branch_input1, add_branch_input2, add_branch_output);
155 -ShiftLeft2 shiftBranch(shiftBranch_input, shiftBranch_output);
156 -ShiftLeft2 shiftJump(shiftJump_input, shiftJump_output);
157 -
158 -initial begin
159 - PC = 32'h00000000;
160 - nextPC = 32'h00000000;
161 -end
162 -
163 -always @(posedge clk) begin
164 -// IF
165 - case(nextPC[0])
166 - 1'b0: PC = nextPC;
167 - 1'b1: PC = nextPC;
168 - endcase
169 -#1;
170 - address = PC;
171 - add_pc4_input = PC;
172 -#1;
173 -// ID
174 - ctrl_opcode <= instr[31:26];
175 - reg_readreg1 <= instr[25:21];
176 - reg_readreg2 <= instr[20:16];
177 - mux_writereg_input1 <= instr[20:16];
178 - mux_writereg_input2 <= instr[15:11];
179 - extend_input <= instr[15:0];
180 - aluctrl_funct <= instr[5:0];
181 - shiftJump_input <= {6'b000000, instr[25:0]};
182 -#1;
183 - mux_writereg_signal <= ctrl_regdst;
184 - aluctrl_aluop <= ctrl_aluop;
185 -
186 -// EX
187 - mux_alu_input1 <= reg_readdata2;
188 - mux_alu_input2 <= extend_output;
189 - mux_alu_signal <= ctrl_alusrc;
190 - shiftBranch_input <= extend_output;
191 -#1;
192 - alu_input1 <= reg_readdata1;
193 - alu_input2 <= mux_alu_output;
194 - alu_control <= aluctrl_sig;
195 - add_branch_input1 <= add_pc4_output;
196 - add_branch_input2 <= shiftBranch_output;
197 -#1;
198 - mux_branch_input1 <= add_pc4_output;
199 - mux_branch_input2 <= add_branch_output;
200 - mux_branch_signal <= ctrl_branch & alu_branch;
201 -#1;
202 -
203 -// MEM
204 - mux_jump_input1 <= mux_branch_output;
205 - mux_jump_input2 <= {add_pc4_output[31:28], shiftJump_output[27:0]};
206 - mux_jump_signal <= ctrl_jump;
207 - mem_addr <= alu_result;
208 - mem_writedata <= reg_readdata2;
209 - mem_memread <= ctrl_memread;
210 - mem_memwrite <= ctrl_memwrite;
211 -#1;
212 -// WB
213 - mux_writedata_input1 <= alu_result;
214 - mux_writedata_input2 <= mem_readdata;
215 - mux_writedata_signal <= ctrl_memtoreg;
216 -#1;
217 - reg_sig_regwrite <= ctrl_regwrite;
218 - reg_writereg1 <= mux_writereg_output;
219 - reg_writedata <= mux_writedata_output;
220 -#1;
221 - nextPC <= mux_jump_output;
222 -end
223 -*/
224 -endmodule
1 -# Reading C:/Modeltech_pe_edu_10.4a/tcl/vsim/pref.tcl
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...@@ -9,308 +9,308 @@ z2 ...@@ -9,308 +9,308 @@ z2
9 cModel Technology 9 cModel Technology
10 dC:/Modeltech_pe_edu_10.4a/examples 10 dC:/Modeltech_pe_edu_10.4a/examples
11 vAdder 11 vAdder
12 -!s110 1590134076 12 +Z0 !s110 1590181223
13 !i10b 1 13 !i10b 1
14 !s100 C]ac0M5ljAN8jKk:YMWUe1 14 !s100 C]ac0M5ljAN8jKk:YMWUe1
15 IPABU2L8BVV2T>WDY4a1F@3 15 IPABU2L8BVV2T>WDY4a1F@3
16 -Z0 VDg1SIo80bB@j0V0VzS_@n1 16 +Z1 VDg1SIo80bB@j0V0VzS_@n1
17 -Z1 dD:/class/Capstone1/KNW_Project2/Project/SingleCycle 17 +Z2 dD:/class/Capstone1/KNW_Project2/Project/SingleCycle
18 w1589585757 18 w1589585757
19 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v 19 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
20 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v 20 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
21 L0 1 21 L0 1
22 -Z2 OP;L;10.4a;61 22 +Z3 OP;L;10.4a;61
23 r1 23 r1
24 !s85 0 24 !s85 0
25 31 25 31
26 -!s108 1590134076.000000 26 +Z4 !s108 1590181223.000000
27 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v| 27 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v|
28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v| 28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v|
29 !s101 -O0 29 !s101 -O0
30 !i113 1 30 !i113 1
31 -Z3 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0 31 +Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
32 n@adder 32 n@adder
33 vALU 33 vALU
34 -!s110 1590179328 34 +R0
35 !i10b 1 35 !i10b 1
36 !s100 :;Xi4U9^j:B2YKA2g;48a2 36 !s100 :;Xi4U9^j:B2YKA2g;48a2
37 Ilz@oO[_i9<DDh^X5Z@MYO2 37 Ilz@oO[_i9<DDh^X5Z@MYO2
38 -R0
39 R1 38 R1
39 +R2
40 w1590179297 40 w1590179297
41 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v 41 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
42 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v 42 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
43 L0 1 43 L0 1
44 -R2 44 +R3
45 r1 45 r1
46 !s85 0 46 !s85 0
47 31 47 31
48 -!s108 1590179328.000000 48 +R4
49 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v| 49 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v|
50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v| 50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v|
51 !s101 -O0 51 !s101 -O0
52 !i113 1 52 !i113 1
53 -R3 53 +R5
54 n@a@l@u 54 n@a@l@u
55 vALUControl 55 vALUControl
56 -Z4 !s110 1590134077 56 +Z6 !s110 1590134077
57 !i10b 1 57 !i10b 1
58 !s100 5M;8KH=?8dC:nP8HEC8AT0 58 !s100 5M;8KH=?8dC:nP8HEC8AT0
59 Ij7f_HKS32W^mlmZIBXe=P0 59 Ij7f_HKS32W^mlmZIBXe=P0
60 -R0
61 R1 60 R1
61 +R2
62 w1589611047 62 w1589611047
63 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v 63 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v
64 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v 64 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v
65 L0 1 65 L0 1
66 -R2 66 +R3
67 r1 67 r1
68 !s85 0 68 !s85 0
69 31 69 31
70 -Z5 !s108 1590134077.000000 70 +Z7 !s108 1590134077.000000
71 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v| 71 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v|
72 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v| 72 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v|
73 !s101 -O0 73 !s101 -O0
74 !i113 1 74 !i113 1
75 -R3 75 +R5
76 n@a@l@u@control 76 n@a@l@u@control
77 vClock 77 vClock
78 -R4 78 +Z8 !s110 1590181224
79 !i10b 1 79 !i10b 1
80 !s100 OWQXV6kDYiT>ChTOoCFa]2 80 !s100 OWQXV6kDYiT>ChTOoCFa]2
81 IQ3e7_okQ4UFF5[gGVRJ]L2 81 IQ3e7_okQ4UFF5[gGVRJ]L2
82 -R0
83 R1 82 R1
83 +R2
84 w1589585780 84 w1589585780
85 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v 85 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
86 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v 86 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
87 L0 1 87 L0 1
88 -R2 88 +R3
89 r1 89 r1
90 !s85 0 90 !s85 0
91 31 91 31
92 -R5 92 +Z9 !s108 1590181224.000000
93 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v| 93 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v|
94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v| 94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v|
95 !s101 -O0 95 !s101 -O0
96 !i113 1 96 !i113 1
97 -R3 97 +R5
98 n@clock 98 n@clock
99 vControl 99 vControl
100 -!s110 1590177655 100 +R8
101 !i10b 1 101 !i10b 1
102 !s100 h4IKEzP5K:837Y_KUcOW]0 102 !s100 h4IKEzP5K:837Y_KUcOW]0
103 I3T=^6M9lNafR2XL8nj12I1 103 I3T=^6M9lNafR2XL8nj12I1
104 -R0
105 R1 104 R1
105 +R2
106 w1590177608 106 w1590177608
107 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v 107 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
108 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v 108 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
109 L0 1 109 L0 1
110 -R2 110 +R3
111 r1 111 r1
112 !s85 0 112 !s85 0
113 31 113 31
114 -!s108 1590177654.000000 114 +R9
115 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v| 115 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v|
116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v| 116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v|
117 !s101 -O0 117 !s101 -O0
118 !i113 1 118 !i113 1
119 -R3 119 +R5
120 n@control 120 n@control
121 vDataMemory 121 vDataMemory
122 -!s110 1590179269 122 +R8
123 !i10b 1 123 !i10b 1
124 !s100 RT9n9HH7ShGYTRk0Zj<MK3 124 !s100 RT9n9HH7ShGYTRk0Zj<MK3
125 InmT0b<BMV7FknI]N:9n7g0 125 InmT0b<BMV7FknI]N:9n7g0
126 -R0
127 R1 126 R1
127 +R2
128 w1590179259 128 w1590179259
129 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v 129 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v
130 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v 130 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v
131 L0 1 131 L0 1
132 -R2 132 +R3
133 r1 133 r1
134 !s85 0 134 !s85 0
135 31 135 31
136 -!s108 1590179269.000000 136 +R9
137 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v| 137 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v|
138 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v| 138 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v|
139 !s101 -O0 139 !s101 -O0
140 !i113 1 140 !i113 1
141 -R3 141 +R5
142 n@data@memory 142 n@data@memory
143 vInstructionMemory 143 vInstructionMemory
144 -!s110 1590180465 144 +Z10 !s110 1590181225
145 !i10b 1 145 !i10b 1
146 !s100 =6Ye0hT1H9KSDP1=FhXga2 146 !s100 =6Ye0hT1H9KSDP1=FhXga2
147 ISLBgfdW;aN8g[2DAo[I992 147 ISLBgfdW;aN8g[2DAo[I992
148 -R0
149 R1 148 R1
149 +R2
150 w1590180454 150 w1590180454
151 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v 151 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
152 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v 152 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
153 L0 1 153 L0 1
154 -R2 154 +R3
155 r1 155 r1
156 !s85 0 156 !s85 0
157 31 157 31
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159 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v| 159 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v|
160 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v| 160 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v|
161 !s101 -O0 161 !s101 -O0
162 !i113 1 162 !i113 1
163 -R3 163 +R5
164 n@instruction@memory 164 n@instruction@memory
165 vMux32bit 165 vMux32bit
166 -R4 166 +R6
167 !i10b 1 167 !i10b 1
168 !s100 6HOE]5bDRSA[<HBJLTnYP0 168 !s100 6HOE]5bDRSA[<HBJLTnYP0
169 InTEk>^`Yjc4Xl2[WnZ3^Y3 169 InTEk>^`Yjc4Xl2[WnZ3^Y3
170 -R0
171 R1 170 R1
172 -Z6 w1589610975
173 -Z7 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
174 -Z8 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
175 -L0 1
176 R2 171 R2
172 +Z12 w1589610975
173 +Z13 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
174 +Z14 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
175 +L0 1
176 +R3
177 r1 177 r1
178 !s85 0 178 !s85 0
179 31 179 31
180 -R5 180 +R7
181 -Z9 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v| 181 +Z15 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
182 -Z10 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v| 182 +Z16 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
183 !s101 -O0 183 !s101 -O0
184 !i113 1 184 !i113 1
185 -R3 185 +R5
186 n@mux32bit 186 n@mux32bit
187 vMux5bit 187 vMux5bit
188 -R4 188 +R6
189 !i10b 1 189 !i10b 1
190 !s100 1oCn>`bHoZ=?A6[JF911T3 190 !s100 1oCn>`bHoZ=?A6[JF911T3
191 I]EmV`Adl6kHglkN9IK>LX2 191 I]EmV`Adl6kHglkN9IK>LX2
192 -R0
193 R1 192 R1
194 -R6
195 -R7
196 -R8
197 -L0 16
198 R2 193 R2
194 +R12
195 +R13
196 +R14
197 +L0 16
198 +R3
199 r1 199 r1
200 !s85 0 200 !s85 0
201 31 201 31
202 -R5 202 +R7
203 -R9 203 +R15
204 -R10 204 +R16
205 !s101 -O0 205 !s101 -O0
206 !i113 1 206 !i113 1
207 -R3 207 +R5
208 n@mux5bit 208 n@mux5bit
209 vRegister 209 vRegister
210 -!s110 1590177077 210 +R10
211 !i10b 1 211 !i10b 1
212 !s100 Bdb0dL`fj[<g;4lO0DTA?2 212 !s100 Bdb0dL`fj[<g;4lO0DTA?2
213 I`9^FTXAAIcP>dnBfah`[e1 213 I`9^FTXAAIcP>dnBfah`[e1
214 -R0
215 R1 214 R1
215 +R2
216 w1590176245 216 w1590176245
217 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v 217 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
218 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v 218 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
219 L0 1 219 L0 1
220 -R2 220 +R3
221 r1 221 r1
222 !s85 0 222 !s85 0
223 31 223 31
224 -!s108 1590177076.000000 224 +R11
225 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v| 225 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
226 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v| 226 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
227 !s101 -O0 227 !s101 -O0
228 !i113 1 228 !i113 1
229 -R3 229 +R5
230 n@register 230 n@register
231 vShiftLeft2 231 vShiftLeft2
232 -R4 232 +R10
233 !i10b 1 233 !i10b 1
234 !s100 eI5Ec:gWMIfN>mTKQIBY93 234 !s100 eI5Ec:gWMIfN>mTKQIBY93
235 IWRY1:Un@<nHGbA7hoKFL[1 235 IWRY1:Un@<nHGbA7hoKFL[1
236 -R0
237 R1 236 R1
237 +R2
238 w1589586193 238 w1589586193
239 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v 239 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
240 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v 240 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
241 L0 1 241 L0 1
242 -R2 242 +R3
243 r1 243 r1
244 !s85 0 244 !s85 0
245 31 245 31
246 -R5 246 +R11
247 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v| 247 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v|
248 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v| 248 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v|
249 !s101 -O0 249 !s101 -O0
250 !i113 1 250 !i113 1
251 -R3 251 +R5
252 n@shift@left2 252 n@shift@left2
253 vSignExtend 253 vSignExtend
254 -Z11 !s110 1590134078 254 +R10
255 !i10b 1 255 !i10b 1
256 !s100 ahVKzC^1fD@70fO3WnVUV0 256 !s100 ahVKzC^1fD@70fO3WnVUV0
257 Izf_2?i[S@:;mKbJ:CXF753 257 Izf_2?i[S@:;mKbJ:CXF753
258 -R0
259 R1 258 R1
259 +R2
260 w1589586199 260 w1589586199
261 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v 261 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
262 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v 262 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
263 L0 1 263 L0 1
264 -R2 264 +R3
265 r1 265 r1
266 !s85 0 266 !s85 0
267 31 267 31
268 -Z12 !s108 1590134078.000000 268 +R11
269 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v| 269 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v|
270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v| 270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v|
271 !s101 -O0 271 !s101 -O0
272 !i113 1 272 !i113 1
273 -R3 273 +R5
274 n@sign@extend 274 n@sign@extend
275 vtest 275 vtest
276 -R11 276 +!s110 1590134078
277 !i10b 1 277 !i10b 1
278 !s100 Sm5D9nHWJl4JV?TA`lU4`0 278 !s100 Sm5D9nHWJl4JV?TA`lU4`0
279 IW:K2A@A@^WBUal;dbVMEN0 279 IW:K2A@A@^WBUal;dbVMEN0
280 -R0
281 R1 280 R1
281 +R2
282 w1589610276 282 w1589610276
283 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v 283 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
284 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v 284 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
285 L0 1 285 L0 1
286 -R2 286 +R3
287 r1 287 r1
288 !s85 0 288 !s85 0
289 31 289 31
290 -R12 290 +!s108 1590134078.000000
291 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v| 291 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v|
292 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v| 292 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v|
293 !s101 -O0 293 !s101 -O0
294 !i113 1 294 !i113 1
295 -R3 295 +R5
296 vtestbench 296 vtestbench
297 -!s110 1590179703 297 +R10
298 !i10b 1 298 !i10b 1
299 !s100 5AnCjSMdS0^a=^L0fjCWj2 299 !s100 5AnCjSMdS0^a=^L0fjCWj2
300 IlnGeUJ27C[a2FGBi<YI?;0 300 IlnGeUJ27C[a2FGBi<YI?;0
301 -R0
302 R1 301 R1
302 +R2
303 w1590179680 303 w1590179680
304 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v 304 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
305 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v 305 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
306 L0 1 306 L0 1
307 -R2 307 +R3
308 r1 308 r1
309 !s85 0 309 !s85 0
310 31 310 31
311 -!s108 1590179703.000000 311 +R11
312 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v| 312 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v|
313 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v| 313 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v|
314 !s101 -O0 314 !s101 -O0
315 !i113 1 315 !i113 1
316 -R3 316 +R5
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