module DataMemory(clk, address, writedata, memread, memwrite, readdata);

input clk;
input[31:0] address, writedata;
input memread, memwrite;
output[31:0] readdata;

reg[31:0] mem[255:0];

assign readdata = memread ? mem[address/4] : writedata;

always @(negedge clk) begin
	if(memwrite==1'b1) begin
		mem[address/4] = writedata;
	end
end

endmodule