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Single Cycle CPU Control Unit, testbench 수정

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module ALU(aluin1, aluin2, aluctrl, aluout, alubranch);
module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch);
input clk;
input[31:0] aluin1, aluin2;
input[3:0] aluctrl;
output reg[31:0] aluout;
......@@ -8,11 +9,14 @@ output alubranch;
reg overflow;
reg[63:0] temp;
reg[31:0] HI, LO; // HI, LO register for multiplication and division.
reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division.
assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
initial begin
temp = 64'h0000000000000000;
tempHI = 32'h00000000;
tempLO = 32'h00000000;
HI = 32'h00000000;
LO = 32'h00000000;
end
......@@ -20,8 +24,8 @@ end
always @(*) begin
overflow = 0;
case(aluctrl)
4'b0000: aluout = aluin1 & aluin2; // and
4'b0001: aluout = aluin1 | aluin2; // or
4'b0000: aluout <= aluin1 & aluin2; // and
4'b0001: aluout <= aluin1 | aluin2; // or
4'b0010: begin // add
aluout = aluin1 + aluin2;
overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
......@@ -37,19 +41,34 @@ case(aluctrl)
end
4'b1000: begin // mult
temp = aluin1 * aluin2;
HI = temp[63:32];
LO = temp[31:0];
tempHI <= temp[63:32];
tempLO <= temp[31:0];
end
4'b1001: begin // div
HI = aluin1 % aluin2;
LO = aluin1 / aluin2;
tempHI <= aluin1 % aluin2;
tempLO <= aluin1 / aluin2;
end
4'b1010: aluout = HI; // mfhi
4'b1011: aluout = LO; // mflo
4'b1100: aluout = ~(aluin1 | aluin2); // nor
4'b1101: aluout = aluin1 ^ aluin2; // xor
default: aluout = 32'b0;
4'b1010: aluout <= HI; // mfhi
4'b1011: aluout <= LO; // mflo
4'b1100: aluout <= ~(aluin1 | aluin2); // nor
4'b1101: aluout <= aluin1 ^ aluin2; // xor
default: aluout <= 32'b0;
endcase
end
always @(negedge clk) begin
case(aluctrl)
4'b1000: begin // mult
HI <= tempHI;
LO <= tempLO;
end
4'b1001: begin // div
HI <= tempHI;
LO <= tempLO;
end
endcase
tempHI = 32'd0;
tempLO = 32'd0;
end
endmodule
......
module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch);
input clk;
input[31:0] aluin1, aluin2;
input[3:0] aluctrl;
output reg[31:0] aluout;
output alubranch;
reg overflow;
reg[63:0] temp;
reg[31:0] HI, LO; // HI, LO register for multiplication and division.
reg[31:0] HI, LO; // HI, LO register for multiplication and division.
assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
initial begin
temp = 64'h0000000000000000;
tempHI = 32'h00000000;
tempLO = 32'h00000000;
HI = 32'h00000000;
LO = 32'h00000000;
end
always @(*) begin
overflow = 0;
case(aluctrl)
4'b0000: aluout <= aluin1 & aluin2; // and
4'b0001: aluout <= aluin1 | aluin2; // or
4'b0010: begin // add
aluout = aluin1 + aluin2;
overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
end
4'b0110: begin // sub
aluout = aluin1 - aluin2;
overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
end
4'b0111: begin // slt
aluout[31:1] = {31{1'b0}};
aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0;
end
4'b1000: begin // mult
temp = aluin1 * aluin2;
tempHI <= temp[63:32];
tempLO <= temp[31:0];
end
4'b1001: begin // div
tempHI <= aluin1 % aluin2;
tempLO <= aluin1 / aluin2;
end
4'b1010: aluout <= HI; // mfhi
4'b1011: aluout <= LO; // mflo
4'b1100: aluout <= ~(aluin1 | aluin2); // nor
4'b1101: aluout <= aluin1 ^ aluin2; // xor
default: aluout <= 32'b0;
endcase
end
always @(negedge clk) begin
case(aluctrl)
4'b1000: begin // mult
HI <= tempHI;
LO <= tempLO;
end
4'b1001: begin // div
HI <= tempHI;
LO <= tempLO;
end
endcase
tempHI = 32'd0;
tempLO = 32'd0;
end
endmodule
module Control(opcode, regdst, regwrite, alusrc, aluop, memread, memwrite, memtoreg, branch, jump);
module Control(opcode, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
input[5:0] opcode;
output reg regdst, jump, branch, memread, memtoreg, memwrite, alusrc, regwrite;
output reg[1:0] aluop;
input[5:0] funct;
output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, branch, jump, jumpreg;
output reg[3:0] aluctrl;
always @(*) begin
case(opcode)
......@@ -10,89 +11,146 @@ always @(*) begin
regdst = 1'b1;
regwrite = 1'b1;
alusrc = 1'b0;
aluop = 2'b10;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
case(funct)
6'b100000: aluctrl = 4'b0010; // add
6'b100001: aluctrl = 4'b0010; // addu
6'b100010: aluctrl = 4'b0110; // sub
6'b100011: aluctrl = 4'b0110; // subu
6'b100100: aluctrl = 4'b0000; // and
6'b100101: aluctrl = 4'b0001; // or
6'b100110: aluctrl = 4'b1101; // xor
6'b011000: aluctrl = 4'b1000; // mult
6'b011001: aluctrl = 4'b1000; // multu
6'b011010: aluctrl = 4'b1001; // div
6'b011011: aluctrl = 4'b1001; // divu
6'b101010: aluctrl = 4'b0111; // slt
6'b101011: aluctrl = 4'b0111; // sltu
6'b010000: aluctrl = 4'b1010; // mfhi
6'b010010: aluctrl = 4'b1011; // mflo
6'b001000: begin // jr
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
jumpreg = 1'b1;
end
default: aluctrl = 4'b1111;
endcase
end
6'b001000: begin // addi
6'b001000: begin // addi instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b001001: begin // addiu
6'b001001: begin // addiu instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000100: begin // beq
6'b001100: begin // andi instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0000; // and
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000100: begin // beq instruction
// regdst = 1'bx; // don't care
regwrite = 1'b0;
alusrc = 1'b0;
aluop = 2'b01;
aluctrl = 4'b0110; // sub
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b1;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000010: begin // jump
6'b000010: begin // jump instruction
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
// aluop = 2'bxx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
jumpreg = 1'b0;
end
6'b100011: begin // lw
6'b100011: begin // lw instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluop = 2'b00;
aluctrl = 4'b0010; // add
memread = 1'b1;
memwrite = 1'b0;
memtoreg = 1'b1;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b101011: begin // sw
6'b101011: begin // sw instruction
regdst = 1'b0;
regwrite = 1'b0;
alusrc = 1'b1;
aluop = 2'b00;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b1;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
default: begin
default: begin // unknown instruction
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluop = 2'b00;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
// branch = 1'bx;
// jump = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
endcase
end
......
module Control(opcode, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
input[5:0] opcode;
input[5:0] funct;
output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, branch, jump, jumpreg;
output reg[3:0] aluctrl;
always @(*) begin
case(opcode)
6'b000000: begin // R type instruction
regdst = 1'b1;
regwrite = 1'b1;
alusrc = 1'b0;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
case(funct)
6'b100000: aluctrl = 4'b0010; // add
6'b100001: aluctrl = 4'b0010; // addu
6'b100010: aluctrl = 4'b0110; // sub
6'b100011: aluctrl = 4'b0110; // subu
6'b100100: aluctrl = 4'b0000; // and
6'b100101: aluctrl = 4'b0001; // or
6'b100110: aluctrl = 4'b1101; // xor
6'b011000: aluctrl = 4'b1000; // mult
6'b011001: aluctrl = 4'b1000; // multu
6'b011010: aluctrl = 4'b1001; // div
6'b011011: aluctrl = 4'b1001; // divu
6'b101010: aluctrl = 4'b0111; // slt
6'b101011: aluctrl = 4'b0111; // sltu
6'b010000: aluctrl = 4'b1010; // mfhi
6'b010010: aluctrl = 4'b1011; // mflo
6'b001000: begin // jr
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b1;
end
default: aluctrl = 4'b1111;
endcase
end
6'b001000: begin // addi instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b001001: begin // addiu instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b001100: begin // andi instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0000; // and
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000100: begin // beq instruction
// regdst = 1'bx; // don't care
regwrite = 1'b0;
alusrc = 1'b0;
aluctrl = 4'b0110; // sub
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b1;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000010: begin // jump instruction
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
jumpreg = 1'b0;
end
6'b100011: begin // lw instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b1;
memwrite = 1'b0;
memtoreg = 1'b1;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b101011: begin // sw instruction
regdst = 1'b0;
regwrite = 1'b0;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b1;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
default: begin // unknown instruction
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
endcase
end
endmodule
module DataMemory(address, writedata, memread, memwrite, readdata);
module DataMemory(clk, address, writedata, memread, memwrite, readdata);
input clk;
input[31:0] address, writedata;
input memread, memwrite;
output[31:0] readdata;
reg[31:0] mem[255:0];
assign readdata = memread ? mem[address/4] : writedata;
assign readdata = memread ? mem[address/4] : 32'd0;
always @(*) begin
always @(negedge clk) begin
if(memwrite==1'b1) begin
mem[address/4] = writedata;
end
......
module DataMemory(clk, address, writedata, memread, memwrite, readdata);
input clk;
input[31:0] address, writedata;
input memread, memwrite;
output[31:0] readdata;
reg[31:0] mem[255:0];
assign readdata = memread ? mem[address/4] : writedata;
always @(negedge clk) begin
if(memwrite==1'b1) begin
mem[address/4] = writedata;
end
end
endmodule
......@@ -20,6 +20,9 @@ instr_mem[10] = 32'd0;
instr_mem[11] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
instr_mem[12] = 32'b10001100000000010000000000111100; // lw $0 $1 60
instr_mem[13] = 32'd0;
instr_mem[14] = 32'b00000000000000000000000000001000; // jr $0
end
......
......@@ -15,7 +15,7 @@ instr_mem[5] = 32'b00000001000010010000000000011000; // mult $8 $9
instr_mem[6] = 32'd0;
instr_mem[7] = 32'b00000000000000000110000000010000; // mfhi $12
instr_mem[8] = 32'b00000000000000000110100000010010; // mflo $13
instr_mem[9] = 32'b10101100000011010000000000111100; // sw $0 $13 15
instr_mem[9] = 32'b10101100000011010000000000111100; // sw $0 $13 60
instr_mem[10] = 32'd0;
instr_mem[11] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
instr_mem[12] = 32'b10001100000000010000000000111100; // lw $0 $1 60
......
D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
{D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v}
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module testbench
Top level modules:
testbench
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Adder
Top level modules:
Adder
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module SignExtend
-- Compiling module DataMemory
Top level modules:
SignExtend
DataMemory
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ALUControl
-- Compiling module ShiftLeft2
Top level modules:
ALUControl
ShiftLeft2
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ShiftLeft2
-- Compiling module InstructionMemory
Top level modules:
ShiftLeft2
InstructionMemory
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module test
-- Compiling module Clock
Top level modules:
test
Clock
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Control
-- Compiling module Adder
Top level modules:
Control
Adder
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ALU
-- Compiling module testbench
Top level modules:
ALU
testbench
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Mux32bit
-- Compiling module Mux5bit
-- Compiling module Register
Top level modules:
Mux32bit
Mux5bit
Register
} {} {}} {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v}
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module DataMemory
-- Compiling module Control
Top level modules:
DataMemory
Control
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Clock
-- Compiling module SignExtend
Top level modules:
Clock
SignExtend
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Register
-- Compiling module ALU
Top level modules:
Register
ALU
} {} {}}
......
This diff is collapsed. Click to expand it.
......@@ -27,3 +27,19 @@ endcase
end
endmodule
module Mux32bit4x1(muxin1, muxin2, muxin3, signal, muxout);
input[31:0] muxin1, muxin2, muxin3;
input[1:0] signal;
output reg[31:0] muxout;
always @(*) begin
case(signal)
2'b00: muxout = muxin1;
2'b01: muxout = muxin2;
2'b11: muxout = muxin3;
endcase
end
endmodule
......
module Register(readin1, readin2, writein, writedata, regwrite, regout1, regout2);
module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
input clk;
input[4:0] readin1, readin2, writein;
input[31:0] writedata;
input regwrite;
......@@ -15,7 +16,7 @@ initial begin
for(i=0; i<32; i=i+1) register[i] = 32'd0;
end
always @(*) begin
always @(negedge clk) begin
if(regwrite == 1'b1 && writein != 5'd0) begin
register[writein] = writedata;
end
......
module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
input clk;
input[4:0] readin1, readin2, writein;
input[31:0] writedata;
input regwrite;
output[31:0] regout1, regout2;
integer i;
reg[31:0] register[31:0];
assign regout1 = register[readin1];
assign regout2 = register[readin2];
initial begin
for(i=0; i<32; i=i+1) register[i] = 32'd0;
end
always @(*) begin
if(regwrite == 1'b1 && writein != 5'd0) begin
register[writein] = writedata;
end
end
endmodule
module testbench;
/*
wire clk; // clock
reg[31:0] PC; // program counter
reg[31:0] instr_address;
wire[31:0] addPC4, addPCbranch, tempPC1, nextPC;
wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
wire[31:0] instr; // loaded instruction.
......@@ -17,10 +17,8 @@ wire alu_branch; // indicator for branch operation.
wire[31:0] mem_readdata; // data from the requested address.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump;
wire[1:0] ctrl_aluop; // control signals.
wire[3:0] aluctrl; // alu control signal.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg;
wire[3:0] ctrl_aluctrl; // control signals.
wire[31:0] extend_output;
......@@ -29,16 +27,16 @@ wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(instr_address, instr);
Register register(instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
ALU alu(reg_readdata1, alu_input2, aluctrl, alu_result, alu_branch);
DataMemory datamem(alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
Control ctrl(instr[31:26], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
ALUControl ALUctrl(instr[5:0], ctrl_aluop, aluctrl);
Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
Mux5bit mux_writereg(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
Mux32bit mux_alu(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
Mux32bit mux_writedata(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC1);
Mux32bit mux_jump(tempPC1, {addPC4[31:28], shiftJump_output[27:0]}, ctrl_jump, nextPC);
Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch);
Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
SignExtend extend(instr[15:0], extend_output);
Adder add_pc4(PC, 32'h00000004, addPC4);
Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
......@@ -57,8 +55,8 @@ always @(posedge clk) begin
instr_address = PC;
end
*/
/*
wire clk; // clock
reg[31:0] PC, nextPC; // program counter
......@@ -222,5 +220,5 @@ always @(posedge clk) begin
#1;
nextPC <= mux_jump_output;
end
*/
endmodule
......
module testbench;
wire clk; // clock
reg[31:0] PC; // program counter
reg[31:0] instr_address;
wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
wire[31:0] instr; // loaded instruction.
wire[4:0] reg_writereg1; // register number for the write data.
wire[31:0] reg_writedata; // data that will be written in the register.
wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
wire[31:0] alu_input2; // input data of ALU.
wire[31:0] alu_result; // result data of ALU.
wire alu_branch; // indicator for branch operation.
wire[31:0] mem_readdata; // data from the requested address.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg;
wire[3:0] ctrl_aluctrl; // control signals.
wire[31:0] extend_output;
wire[31:0] shiftBranch_output;
wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(instr_address, instr);
Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
Control ctrl(instr[31:26], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
Mux5bit mux_writereg(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
Mux32bit mux_alu(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
Mux32bit mux_writedata(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch);
Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
SignExtend extend(instr[15:0], extend_output);
Adder add_pc4(PC, 32'h00000004, addPC4);
Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
initial begin
PC = 32'h00000000;
end
always @(posedge clk) begin
case(nextPC[31]) // if nextPC is available, PC = nextPC.
1'b0: PC = nextPC;
1'b1: PC = nextPC;
endcase
instr_address = PC;
end
/*
wire clk; // clock
reg[31:0] PC, nextPC; // program counter
// Instruction Memory (IM)
reg[31:0] address; // instruction address. input of IM.
wire[31:0] instr; // loaded instruction. output of IM
// Register
reg[4:0] reg_readreg1, reg_readreg2; // register numbers of the read data. input of register.
reg[4:0] reg_writereg1; // register number for the write data. input of register.
reg[31:0] reg_writedata; // data that will be written in the register. input of register.
reg reg_sig_regwrite; // regwrite control signal. input of register
wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. outputs of register.
// ALU
reg[31:0] alu_input1, alu_input2; // input data of ALU. inputs of ALU.
reg[3:0] alu_control; // ALU control signal. input of ALU.
wire[31:0] alu_result; // result data of ALU. output of ALU.
wire alu_branch; // indicator for branch operation. output of ALU.
//Data Memory (DM)
reg[31:0] mem_addr; // address of the read data. input of DM.
reg[31:0] mem_writedata; // data that will be written in the memory. input of DM.
reg mem_memread, mem_memwrite; // control signals for DM. input of DM.
wire[31:0] mem_readdata; // data from the requested address. output of DM.
// Control Unit
reg[5:0] ctrl_opcode; // opcode of the instruction. input of control unit.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread; // ??
wire ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump; // ??? control signals outputs of control unit.
wire[1:0] ctrl_aluop; // ??
// ALU Control Unit
reg[5:0] aluctrl_funct; // function code of the R type instructions. input of ALU control unit.
reg[1:0] aluctrl_aluop; // aluop signal. input of ALU control unit.
wire[3:0] aluctrl_sig; // alu control signal. output of ALU control unit.
// Multiplexer (Mux)
// mux_writereg Mux for Write Register.
reg[4:0] mux_writereg_input1, mux_writereg_input2;
reg mux_writereg_signal;
wire[4:0] mux_writereg_output;
// mux_alu Mux for ALU input 2.
reg[31:0] mux_alu_input1, mux_alu_input2;
reg mux_alu_signal;
wire[31:0] mux_alu_output;
// mux_writedata Mux for Write Data of Register.
reg[31:0] mux_writedata_input1, mux_writedata_input2;
reg mux_writedata_signal;
wire[31:0] mux_writedata_output;
// mux_branch Mux for Branch
reg[31:0] mux_branch_input1, mux_branch_input2;
reg mux_branch_signal;
wire[31:0] mux_branch_output;
// mux_jump Mux for Jump
reg[31:0] mux_jump_input1, mux_jump_input2;
reg mux_jump_signal;
wire[31:0] mux_jump_output;
// Sign Extend
reg[15:0] extend_input;
wire[31:0] extend_output;
// Adder
// add_pc4
reg[31:0] add_pc4_input; // input2 is 4.
wire[31:0] add_pc4_output;
// add_branch
reg[31:0] add_branch_input1, add_branch_input2;
wire[31:0] add_branch_output;
// Shift Left 2
// shiftBranch ShiftLeft2 which is used for Branch instructions.
reg[31:0] shiftBranch_input;
wire[31:0] shiftBranch_output;
// shiftJump ShiftLeft2 which is used for Jump instructions.
reg[31:0] shiftJump_input;
wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(address, instr);
Register register(reg_readreg1, reg_readreg2, reg_writereg1, reg_writedata, reg_sig_regwrite, reg_readdata1, reg_readdata2);
ALU alu(alu_input1, alu_input2, alu_control, alu_result, alu_branch);
DataMemory datamem(mem_addr, mem_writedata, mem_memread, mem_memwrite, mem_readdata);
Control ctrl(ctrl_opcode, ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
ALUControl aluctrl(aluctrl_funct, aluctrl_aluop, aluctrl_sig);
Mux5bit mux_writereg(mux_writereg_input1, mux_writereg_input2, mux_writereg_signal, mux_writereg_output);
Mux32bit mux_alu(mux_alu_input1, mux_alu_input2, mux_alu_signal, mux_alu_output);
Mux32bit mux_writedata(mux_writedata_input1, mux_writedata_input2, mux_writedata_signal, mux_writedata_output);
Mux32bit mux_branch(mux_branch_input1, mux_branch_input2, mux_branch_signal, mux_branch_output);
Mux32bit mux_jump(mux_jump_input1, mux_jump_input2, mux_jump_signal, mux_jump_output);
SignExtend extend(extend_input, extend_output);
Adder add_pc4(add_pc4_input, 32'h00000004, add_pc4_output);
Adder add_branch(add_branch_input1, add_branch_input2, add_branch_output);
ShiftLeft2 shiftBranch(shiftBranch_input, shiftBranch_output);
ShiftLeft2 shiftJump(shiftJump_input, shiftJump_output);
initial begin
PC = 32'h00000000;
nextPC = 32'h00000000;
end
always @(posedge clk) begin
// IF
case(nextPC[0])
1'b0: PC = nextPC;
1'b1: PC = nextPC;
endcase
#1;
address = PC;
add_pc4_input = PC;
#1;
// ID
ctrl_opcode <= instr[31:26];
reg_readreg1 <= instr[25:21];
reg_readreg2 <= instr[20:16];
mux_writereg_input1 <= instr[20:16];
mux_writereg_input2 <= instr[15:11];
extend_input <= instr[15:0];
aluctrl_funct <= instr[5:0];
shiftJump_input <= {6'b000000, instr[25:0]};
#1;
mux_writereg_signal <= ctrl_regdst;
aluctrl_aluop <= ctrl_aluop;
// EX
mux_alu_input1 <= reg_readdata2;
mux_alu_input2 <= extend_output;
mux_alu_signal <= ctrl_alusrc;
shiftBranch_input <= extend_output;
#1;
alu_input1 <= reg_readdata1;
alu_input2 <= mux_alu_output;
alu_control <= aluctrl_sig;
add_branch_input1 <= add_pc4_output;
add_branch_input2 <= shiftBranch_output;
#1;
mux_branch_input1 <= add_pc4_output;
mux_branch_input2 <= add_branch_output;
mux_branch_signal <= ctrl_branch & alu_branch;
#1;
// MEM
mux_jump_input1 <= mux_branch_output;
mux_jump_input2 <= {add_pc4_output[31:28], shiftJump_output[27:0]};
mux_jump_signal <= ctrl_jump;
mem_addr <= alu_result;
mem_writedata <= reg_readdata2;
mem_memread <= ctrl_memread;
mem_memwrite <= ctrl_memwrite;
#1;
// WB
mux_writedata_input1 <= alu_result;
mux_writedata_input2 <= mem_readdata;
mux_writedata_signal <= ctrl_memtoreg;
#1;
reg_sig_regwrite <= ctrl_regwrite;
reg_writereg1 <= mux_writereg_output;
reg_writedata <= mux_writedata_output;
#1;
nextPC <= mux_jump_output;
end
*/
endmodule
# Reading C:/Modeltech_pe_edu_10.4a/tcl/vsim/pref.tcl
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......@@ -9,83 +9,83 @@ z2
cModel Technology
dC:/Modeltech_pe_edu_10.4a/examples
vAdder
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!s101 -O0
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!s101 -O0
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R0
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!s100 OWQXV6kDYiT>ChTOoCFa]2
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8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
L0 1
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......@@ -94,86 +94,86 @@ R5
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v|
!s101 -O0
!i113 1
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vControl
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!s85 0
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!s108 1590179269.000000
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!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v|
!s101 -O0
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L0 1
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Z8 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
L0 1
R3
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r1
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......@@ -182,20 +182,20 @@ Z9 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
Z10 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
!s101 -O0
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vMux5bit
R0
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!i10b 1
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......@@ -204,42 +204,42 @@ R9
R10
!s101 -O0
!i113 1
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n@mux5bit
vRegister
R0
!s110 1590177077
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R1
R2
w1589611738
w1590176245
8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
L0 1
R3
R2
r1
!s85 0
31
R5
!s108 1590177076.000000
!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
!s101 -O0
!i113 1
R4
R3
n@register
vShiftLeft2
R0
R4
!i10b 1
!s100 eI5Ec:gWMIfN>mTKQIBY93
IWRY1:Un@<nHGbA7hoKFL[1
R0
R1
R2
w1589586193
8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
L0 1
R3
R2
r1
!s85 0
31
......@@ -248,42 +248,42 @@ R5
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v|
!s101 -O0
!i113 1
R4
R3
n@shift@left2
vSignExtend
Z11 !s110 1589714637
Z11 !s110 1590134078
!i10b 1
!s100 ahVKzC^1fD@70fO3WnVUV0
Izf_2?i[S@:;mKbJ:CXF753
R0
R1
R2
w1589586199
8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
L0 1
R3
R2
r1
!s85 0
31
Z12 !s108 1589714637.000000
Z12 !s108 1590134078.000000
!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v|
!s101 -O0
!i113 1
R4
R3
n@sign@extend
vtest
R11
!i10b 1
!s100 Sm5D9nHWJl4JV?TA`lU4`0
IW:K2A@A@^WBUal;dbVMEN0
R0
R1
R2
w1589610276
8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
L0 1
R3
R2
r1
!s85 0
31
......@@ -292,25 +292,25 @@ R12
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v|
!s101 -O0
!i113 1
R4
R3
vtestbench
R11
!s110 1590179703
!i10b 1
!s100 z4HT6K50i`GDM7=h[az0B1
Ik;o@8lk>glJB?9fgUD_;W3
!s100 5AnCjSMdS0^a=^L0fjCWj2
IlnGeUJ27C[a2FGBi<YI?;0
R0
R1
R2
w1589625001
w1590179680
8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
L0 1
R3
R2
r1
!s85 0
31
R12
!s108 1590179703.000000
!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v|
!s101 -O0
!i113 1
R4
R3
......
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