Mux.v.bak
710 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
module Mux32bit(muxin1, muxin2, signal, muxout);
input[31:0] muxin1, muxin2;
input signal;
output reg[31:0] muxout;
always @(*) begin
case(signal)
1'b0: muxout = muxin1;
1'b1: muxout = muxin2;
endcase
end
endmodule
module Mux5bit(muxin1, muxin2, signal, muxout);
input[4:0] muxin1, muxin2;
input signal;
output reg[4:0] muxout;
always @(*) begin
case(signal)
1'b0: muxout = muxin1;
1'b1: muxout = muxin2;
endcase
end
endmodule
module Mux32bit4x1(muxin1, muxin2, muxin3, signal, muxout);
input[31:0] muxin1, muxin2, muxin3;
input[1:0] signal;
output reg[31:0] muxout;
always @(*) begin
case(signal)
2'b00: muxout = muxin1;
2'b01: muxout = muxin2;
2'b11: muxout = muxin3;
endcase
end
endmodule