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오타 수정 및 stall 기능 추가(data hazard)

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Showing 23 changed files with 344 additions and 197 deletions
1 module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch); 1 module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch);
2 -
3 input clk; 2 input clk;
4 input[31:0] aluin1, aluin2; 3 input[31:0] aluin1, aluin2;
5 input[3:0] aluctrl; 4 input[3:0] aluctrl;
6 output reg[31:0] aluout; 5 output reg[31:0] aluout;
7 -// output alubranch;
8 output reg[5:0] alubranch; 6 output reg[5:0] alubranch;
9 7
10 reg overflow; 8 reg overflow;
...@@ -12,8 +10,6 @@ reg[63:0] temp; ...@@ -12,8 +10,6 @@ reg[63:0] temp;
12 reg[31:0] HI, LO; // HI, LO register for multiplication and division. 10 reg[31:0] HI, LO; // HI, LO register for multiplication and division.
13 reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division. 11 reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division.
14 12
15 -// assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
16 -
17 initial begin 13 initial begin
18 temp = 64'h0000000000000000; 14 temp = 64'h0000000000000000;
19 tempHI = 32'h00000000; 15 tempHI = 32'h00000000;
...@@ -23,8 +19,9 @@ initial begin ...@@ -23,8 +19,9 @@ initial begin
23 end 19 end
24 20
25 always @(*) begin 21 always @(*) begin
26 -overflow = 0; 22 + overflow = 1'b0;
27 -case(aluctrl) 23 + alubranch = 6'b0;
24 + case(aluctrl)
28 4'b0000: aluout <= aluin1 & aluin2; // and 25 4'b0000: aluout <= aluin1 & aluin2; // and
29 4'b0001: aluout <= aluin1 | aluin2; // or 26 4'b0001: aluout <= aluin1 | aluin2; // or
30 4'b0010: begin // add 27 4'b0010: begin // add
...@@ -34,12 +31,12 @@ case(aluctrl) ...@@ -34,12 +31,12 @@ case(aluctrl)
34 4'b0110: begin // sub 31 4'b0110: begin // sub
35 aluout = aluin1 - aluin2; 32 aluout = aluin1 - aluin2;
36 overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection. 33 overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
37 - alubranch[0] = (aluout == 32'd0) ? 1'b1 : 1'b0; // beq 34 + alubranch[0] = (aluout == 32'h00000000) ? 1'b1 : 1'b0; // beq
38 - alubranch[1] = (aluout != 32'd0) ? 1'b1 : 1'b0; // bne 35 + alubranch[1] = (aluout != 32'h00000000) ? 1'b1 : 1'b0; // bne
39 - alubranch[2] = (aluin1 > 32'd0) ? 1'b1 : 1'b0; // bgtz 36 + alubranch[2] = (aluin1 > 32'h00000000) ? 1'b1 : 1'b0; // bgtz
40 - alubranch[3] = (aluin1 < 32'd0) ? 1'b1 : 1'b0; // bltz 37 + alubranch[3] = (aluin1 < 32'h00000000) ? 1'b1 : 1'b0; // bltz
41 - alubranch[4] = (aluin1 >= 32'd0) ? 1'b1 : 1'b0; // bgez 38 + alubranch[4] = (aluin1 >= 32'h00000000) ? 1'b1 : 1'b0; // bgez
42 - alubranch[5] = (aluin1 <= 32'd0) ? 1'b1 : 1'b0; // blez 39 + alubranch[5] = (aluin1 <= 32'h00000000) ? 1'b1 : 1'b0; // blez
43 end 40 end
44 41
45 4'b0111: begin // slt 42 4'b0111: begin // slt
...@@ -59,8 +56,8 @@ case(aluctrl) ...@@ -59,8 +56,8 @@ case(aluctrl)
59 4'b1011: aluout <= LO; // mflo 56 4'b1011: aluout <= LO; // mflo
60 4'b1100: aluout <= ~(aluin1 | aluin2); // nor 57 4'b1100: aluout <= ~(aluin1 | aluin2); // nor
61 4'b1101: aluout <= aluin1 ^ aluin2; // xor 58 4'b1101: aluout <= aluin1 ^ aluin2; // xor
62 - default: aluout <= 32'b0; 59 + default: aluout <= 32'h00000000;
63 -endcase 60 + endcase
64 end 61 end
65 62
66 always @(negedge clk) begin 63 always @(negedge clk) begin
......
1 module Adder(adderinput1, adderinput2, adderoutput); 1 module Adder(adderinput1, adderinput2, adderoutput);
2 -
3 input[31:0] adderinput1, adderinput2; 2 input[31:0] adderinput1, adderinput2;
4 output[31:0] adderoutput; 3 output[31:0] adderoutput;
5 4
......
1 module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg); 1 module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
2 -
3 input[5:0] opcode; 2 input[5:0] opcode;
4 input[4:0] rt; 3 input[4:0] rt;
5 input[5:0] funct; 4 input[5:0] funct;
......
1 module DataMemory(clk, address, writedata, memread, memwrite, readdata); 1 module DataMemory(clk, address, writedata, memread, memwrite, readdata);
2 -
3 input clk; 2 input clk;
4 input[31:0] address, writedata; 3 input[31:0] address, writedata;
5 input memread, memwrite; 4 input memread, memwrite;
6 -output[31:0] readdata; 5 +output reg[31:0] readdata;
7 6
7 +integer i;
8 reg[31:0] mem[255:0]; 8 reg[31:0] mem[255:0];
9 9
10 -assign readdata = memread ? mem[address/4] : 32'd0; 10 +initial begin
11 + for(i=0; i<256; i=i+1) mem[i] = 32'd0;
12 +end
11 13
12 always @(negedge clk) begin 14 always @(negedge clk) begin
15 + if(memread== 1'b1) begin
16 + readdata = mem[address/4];
17 + end
13 if(memwrite==1'b1) begin 18 if(memwrite==1'b1) begin
14 mem[address/4] = writedata; 19 mem[address/4] = writedata;
15 end 20 end
......
1 -/* Not Finished */
2 -module Stall(clk, in_readreg_num1, in_readreg_num2, in_writereg_num);
3 -
4 -input clk;
5 -input[4:0] in_readreg_num1, in_readreg_num2, in_writereg_num;
6 -
7 -reg[4:0] writeregs;
8 -
9 -endmodule
10 -
11 -
...@@ -7,24 +7,39 @@ reg[31:0] instr_mem[127:0]; ...@@ -7,24 +7,39 @@ reg[31:0] instr_mem[127:0];
7 7
8 initial begin 8 initial begin
9 instr_mem[0] = 32'd0; 9 instr_mem[0] = 32'd0;
10 -instr_mem[1] = 32'b00100100000010000000000011111111; // addi, $0 $8 255 10 +instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
11 -instr_mem[2] = 32'b00000001000010000100100000100000; // add, $8 $8 $9 11 +instr_mem[2] = 32'd0;
12 -instr_mem[3] = 32'b00000001000000000101000000100000; // add, $8 $0 $10 12 +instr_mem[3] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
13 -instr_mem[4] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1 13 +instr_mem[4] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
14 -instr_mem[5] = 32'd0; 14 +instr_mem[5] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
15 -instr_mem[6] = 32'b00000001000010010000000000011000; // mult, $8 $9 15 +instr_mem[6] = 32'b00100100000011010000000000000011; // addi, $0 $13 3
16 -instr_mem[7] = 32'd0; 16 +instr_mem[7] = 32'b00100100000010010000000000000001; // addi, $0 $9 1
17 -instr_mem[8] = 32'b00000000000000000110000000010000; // mfhi, $12 17 +instr_mem[8] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
18 -instr_mem[9] = 32'b00000000000000000110100000010010; // mflo, $13 18 +instr_mem[9] = 32'd0;
19 -instr_mem[10] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
20 -instr_mem[11] = 32'd0;
21 -instr_mem[12] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
22 -instr_mem[13] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
23 -instr_mem[14] = 32'd0;
24 -instr_mem[15] = 32'b00000000000000000000000000001000; // jr, $0
25 -
26 end 19 end
20 +/*
21 +initial begin
22 +out_clk = 1'b0;
27 23
24 +instr_mem[0] = 32'd0;
25 +instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
26 +instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
27 +instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9
28 +instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10
29 +instr_mem[5] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1
30 +instr_mem[6] = 32'd0;
31 +instr_mem[7] = 32'b00000001000010010000000000011000; // mult, $8 $9
32 +instr_mem[8] = 32'd0;
33 +instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12
34 +instr_mem[10] = 32'b00000000000000000110100000010010; // mflo, $13
35 +instr_mem[11] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
36 +instr_mem[12] = 32'd0;
37 +instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
38 +instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
39 +instr_mem[15] = 32'd0;
40 +instr_mem[16] = 32'b00000000000000000000000000001000; // jr, $0
41 +end
42 +*/
28 always @ (*) begin 43 always @ (*) begin
29 instruction = instr_mem[address/4]; 44 instruction = instr_mem[address/4];
30 end 45 end
......
1 -D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v 1 +D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module testbench 3 +-- Compiling module test
4 +-- Compiling module testA
5 +-- Compiling module testB
6 +-- Compiling module testPC
4 7
5 Top level modules: 8 Top level modules:
6 - testbench 9 + test
7 10
8 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v 11 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 12 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 --- Compiling module test 13 +-- Compiling module testbench
11 --- Compiling module testA
12 14
13 Top level modules: 15 Top level modules:
14 - test 16 + testbench
15 17
16 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 18 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
17 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 19 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -41,6 +43,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -41,6 +43,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
41 Top level modules: 43 Top level modules:
42 Register 44 Register
43 45
46 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
47 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
48 +-- Compiling module MIPS_Pipeline
49 +
50 +Top level modules:
51 + MIPS_Pipeline
52 +
44 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 53 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
45 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 54 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
46 -- Compiling module IF_ID 55 -- Compiling module IF_ID
...@@ -56,14 +65,7 @@ Top level modules: ...@@ -56,14 +65,7 @@ Top level modules:
56 MEM_WB 65 MEM_WB
57 PCcounter 66 PCcounter
58 67
59 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 68 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
60 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
61 --- Compiling module MIPS_Pipeline
62 -
63 -Top level modules:
64 - MIPS_Pipeline
65 -
66 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
67 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 69 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
68 -- Compiling module Stall 70 -- Compiling module Stall
69 71
...@@ -84,6 +86,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -84,6 +86,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
84 Top level modules: 86 Top level modules:
85 Control 87 Control
86 88
89 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
90 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
91 +-- Compiling module ALU
92 +
93 +Top level modules:
94 + ALU
95 +
87 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 96 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
88 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 97 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
89 -- Compiling module Mux5bit 98 -- Compiling module Mux5bit
...@@ -95,12 +104,12 @@ Top level modules: ...@@ -95,12 +104,12 @@ Top level modules:
95 Mux32bit 104 Mux32bit
96 MuxBranchSignal 105 MuxBranchSignal
97 106
98 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 107 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
99 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 108 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
100 --- Compiling module ALU 109 +-- Compiling module ShiftLeft2
101 110
102 Top level modules: 111 Top level modules:
103 - ALU 112 + ShiftLeft2
104 113
105 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} 114 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
106 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 115 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -109,14 +118,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -109,14 +118,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
109 Top level modules: 118 Top level modules:
110 DataMemory 119 DataMemory
111 120
112 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 121 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
113 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
114 --- Compiling module ShiftLeft2
115 -
116 -Top level modules:
117 - ShiftLeft2
118 -
119 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
120 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 122 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
121 -- Compiling module Clock 123 -- Compiling module Clock
122 124
......
This diff is collapsed. Click to expand it.
1 // Test Required 1 // Test Required
2 module MIPS_Pipeline; 2 module MIPS_Pipeline;
3 3
4 -wire clk; // clock 4 +wire clk;
5 +wire stallsignal;
5 wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC; 6 wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
6 7
7 wire[31:0] instr; // loaded instruction. 8 wire[31:0] instr; // loaded instruction.
...@@ -46,14 +47,21 @@ wire memwb_regwrite, memwb_memtoreg, memwb_jump; ...@@ -46,14 +47,21 @@ wire memwb_regwrite, memwb_memtoreg, memwb_jump;
46 wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump; 47 wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;
47 48
48 49
50 +
51 +wire tempstall;
52 +assign tempstall = 1'b0;
53 +
49 Clock clock(clk); 54 Clock clock(clk);
50 -PCcounter pccounter(clk, nextPC, instr_address); 55 +PCcounter pccounter(clk, stallsignal, nextPC, instr_address);
56 +Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite,
57 + ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,
58 + stallsignal);
51 59
52 // Instruction Fetch 60 // Instruction Fetch
53 InstructionMemory instrmem(instr_address, instr); 61 InstructionMemory instrmem(instr_address, instr);
54 -Adder add_pc4(PC, 32'h00000004, addPC4); 62 +Adder add_pc4(instr_address, 32'h00000004, addPC4);
55 63
56 -IF_ID ifid(clk, instr, addPC4, 64 +IF_ID ifid(clk, stallsignal, instr, addPC4,
57 ifid_instr, ifid_PC_4); 65 ifid_instr, ifid_PC_4);
58 66
59 // Instruction Decode 67 // Instruction Decode
...@@ -63,15 +71,15 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re ...@@ -63,15 +71,15 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re
63 SignExtend extend(ifid_instr[15:0], extend_output); 71 SignExtend extend(ifid_instr[15:0], extend_output);
64 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output); 72 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
65 73
66 -ID_EX idex(clk, reg_writereg1, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 74 +ID_EX idex(clk, stallsignal, reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg,
67 - reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, ifid_instr[25:21], ifid_instr[20:16], 75 + reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output,
68 - idex_writereg1, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 76 + idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg,
69 - idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump, idex_readreg_num1, idex_readreg_num2); 77 + idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
70 78
71 // Execute 79 // Execute
72 -Mux32bit mux_alusrc(idex_readdata2, idex_extend, idex_alusrc, alu_input2); 80 +Mux32bit mux_alusrc(idex_readdata2, idex_extenddata, idex_alusrc, alu_input2);
73 ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch); 81 ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch);
74 -ShiftLeft2 shiftBranch(idex_extend, shiftBranch_output); 82 +ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
75 Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch); 83 Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
76 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal); 84 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal);
77 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump); 85 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump);
...@@ -86,80 +94,16 @@ DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exm ...@@ -86,80 +94,16 @@ DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exm
86 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch); 94 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch);
87 95
88 MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 96 MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump,
89 - exmem_aluresult, mem_readdata, tempPC_branch, exmem_PCjump, 97 + exmem_aluresult, mem_readdata, exmem_PCjump, tempPC_branch,
90 memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 98 memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump,
91 - memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump); 99 + memwb_aluresult, memwb_memreaddata, memwb_PCjump, memwb_PCbranch);
92 100
93 // Writeback 101 // Writeback
94 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, reg_writedata); 102 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, reg_writedata);
95 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC); 103 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC);
96 104
97 105
98 -
99 -
100 -always @(posedge clk) begin
101 -
102 -end
103 -
104 -/*
105 -wire clk; // clock
106 -reg[31:0] PC, instr_address;
107 -
108 -// IF - ID
109 -wire[31:0] if_id_instruction, if_id_pc_4;
110 -
111 -// ID - EX
112 -wire[31:0] id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump;
113 -wire[4:0] id_ex_writereg, id_hh_readreg1, id_hh_readreg2;
114 -wire id_ex_regwrite, id_ex_alusrc, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg;
115 -wire[3:0] id_ex_aluctrl;
116 -
117 -// EX - MEM
118 -wire[31:0] ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch;
119 -wire[4:0] ex_mem_writereg;
120 -wire ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump;
121 -
122 -// MEM - WB
123 -wire[4:0] mem_wb_writereg_num;
124 -wire mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump;
125 -wire[31:0] mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump;
126 -
127 -// WB - etc.
128 -wire wb_id_regwrite;
129 -wire[4:0] wb_id_writereg;
130 -wire[31:0] wb_id_reg_writedata;
131 -wire[31:0] wb_nextPC;
132 -
133 -Clock clock(clk);
134 -
135 -InstructionFetch IF(clk, PC, if_id_instruction, if_id_pc_4);
136 -
137 -InstructionDecode ID(clk, if_id_instruction, if_id_pc_4, wb_id_writereg, wb_id_reg_writedata, wb_id_regwrite,
138 - id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
139 - id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump);
140 -
141 -Execute EX(clk, id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
142 - id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump,
143 - ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump,
144 - ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch);
145 -
146 -Mem MEM(clk, ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump,
147 - ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch,
148 - mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump);
149 -
150 -WriteBack WB(clk, mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump,
151 - wb_id_regwrite, wb_id_writereg, wb_id_reg_writedata, wb_nextPC);
152 -
153 -initial begin
154 - PC = 32'hfffffffc;
155 -end
156 -
157 always @(posedge clk) begin 106 always @(posedge clk) begin
158 - instr_address = PC;
159 end 107 end
160 108
161 -always @(negedge clk) begin
162 - PC = PC + 4;
163 -end
164 -*/
165 endmodule 109 endmodule
......
...@@ -26,12 +26,14 @@ wire[31:0] extend_output; ...@@ -26,12 +26,14 @@ wire[31:0] extend_output;
26 wire[31:0] shiftBranch_output; 26 wire[31:0] shiftBranch_output;
27 wire[31:0] shiftJump_output; 27 wire[31:0] shiftJump_output;
28 28
29 +
29 Clock clock(clk); 30 Clock clock(clk);
30 InstructionMemory instrmem(instr_address, instr); 31 InstructionMemory instrmem(instr_address, instr);
31 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2); 32 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
32 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch); 33 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
33 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata); 34 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
34 Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg); 35 Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
36 +
35 Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1); 37 Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
36 MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal); 38 MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal);
37 Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2); 39 Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
......
...@@ -44,3 +44,4 @@ always @(*) begin ...@@ -44,3 +44,4 @@ always @(*) begin
44 end 44 end
45 45
46 endmodule 46 endmodule
47 +
......
1 -module IF_ID(clk, in_instruction, in_PC_4, 1 +module IF_ID(clk, stall, in_instruction, in_PC_4,
2 out_instruction, out_PC_4); 2 out_instruction, out_PC_4);
3 -input clk; 3 +input clk, stall;
4 +
4 input[31:0] in_instruction, in_PC_4; 5 input[31:0] in_instruction, in_PC_4;
6 +
5 output reg[31:0] out_instruction, out_PC_4; 7 output reg[31:0] out_instruction, out_PC_4;
6 8
9 +reg[31:0] temp_instruction, temp_PC_4;
10 +
11 +reg stallfinished;
12 +
13 +initial begin
14 + stallfinished = 1'b0;
15 +end
16 +
7 always @(posedge clk) begin 17 always @(posedge clk) begin
18 +
19 + if(stall == 1'b1) begin
20 + out_instruction <= 32'h00000000;
21 + out_PC_4 <= 32'h00000000;
22 + end
23 + else if(stallfinished == 1'b1) begin
24 + out_instruction <= temp_instruction;
25 + out_PC_4 <= temp_PC_4;
26 +
27 + stallfinished = 1'b0;
28 + end
29 + else begin
8 out_instruction <= in_instruction; 30 out_instruction <= in_instruction;
9 out_PC_4 <= in_PC_4; 31 out_PC_4 <= in_PC_4;
32 + end
33 +end
34 +
35 +always @(posedge stall) begin
36 + temp_instruction <= out_instruction;
37 + temp_PC_4 <= out_PC_4;
38 +end
39 +always @(negedge stall) begin
40 + stallfinished = 1'b1;
10 end 41 end
11 endmodule 42 endmodule
12 43
13 44
14 -module ID_EX(clk, in_writereg_num, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 45 +module ID_EX(clk, stall, in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg,
15 - in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2, 46 + in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump,
16 - out_writereg_num, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 47 + out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg,
17 - out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2); 48 + out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
18 -input clk; 49 +input clk, stall;
19 -input[4:0] in_writereg_num; 50 +
20 -input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg; 51 +input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
52 +input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg;
21 input[3:0] in_aluctrl; 53 input[3:0] in_aluctrl;
22 -input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2; 54 +input[2:0] in_branch;
23 -output reg[4:0] out_writereg_num; 55 +input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump;
24 -output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg; 56 +
57 +output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2;
58 +output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg;
25 output reg[3:0] out_aluctrl; 59 output reg[3:0] out_aluctrl;
26 -output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2; 60 +output reg[2:0] out_branch;
61 +output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
27 62
63 +reg stallfinished;
64 +
65 +initial begin
66 + stallfinished = 1'b0;
67 +end
28 always @(posedge clk) begin 68 always @(posedge clk) begin
69 + if(stall == 1'b1) begin
70 + out_writereg_num <= 5'b00000;
71 + out_readreg_num1 <= 5'b00000;
72 + out_readreg_num2 <= 5'b00000;
73 +
74 + out_regwrite <= 1'b0;
75 + out_alusrc <= 1'b0;
76 + out_aluctrl <= 4'b0000;
77 + out_memread <= 1'b0;
78 + out_memwrite <= 1'b0;
79 + out_memtoreg <= 1'b0;
80 + out_branch <= 3'b000;
81 + out_jump <= 1'b0;
82 + out_jumpreg <= 1'b0;
83 +
84 + out_readdata1 <= 32'h00000000;
85 + out_readdata2 <= 32'h00000000;
86 + out_extenddata <= 32'h00000000;
87 + out_PC_4 <= 32'h00000000;
88 + out_tempPCjump <= 32'h00000000;
89 + end
90 + else if(stallfinished == 1'b1) begin
91 + out_writereg_num <= 5'b00000;
92 + out_readreg_num1 <= 5'b00000;
93 + out_readreg_num2 <= 5'b00000;
94 +
95 + out_regwrite <= 1'b0;
96 + out_alusrc <= 1'b0;
97 + out_aluctrl <= 4'b0000;
98 + out_memread <= 1'b0;
99 + out_memwrite <= 1'b0;
100 + out_memtoreg <= 1'b0;
101 + out_branch <= 3'b000;
102 + out_jump <= 1'b0;
103 + out_jumpreg <= 1'b0;
104 +
105 + out_readdata1 <= 32'h00000000;
106 + out_readdata2 <= 32'h00000000;
107 + out_extenddata <= 32'h00000000;
108 + out_PC_4 <= 32'h00000000;
109 + out_tempPCjump <= 32'h00000000;
110 +
111 + stallfinished = 1'b0;
112 + end
113 + else begin
29 out_writereg_num <= in_writereg_num; 114 out_writereg_num <= in_writereg_num;
115 + out_readreg_num1 <= in_readreg_num1;
116 + out_readreg_num2 <= in_readreg_num2;
117 +
30 out_regwrite <= in_regwrite; 118 out_regwrite <= in_regwrite;
31 out_alusrc <= in_alusrc; 119 out_alusrc <= in_alusrc;
32 out_aluctrl <= in_aluctrl; 120 out_aluctrl <= in_aluctrl;
...@@ -40,11 +128,14 @@ always @(posedge clk) begin ...@@ -40,11 +128,14 @@ always @(posedge clk) begin
40 out_readdata1 <= in_readdata1; 128 out_readdata1 <= in_readdata1;
41 out_readdata2 <= in_readdata2; 129 out_readdata2 <= in_readdata2;
42 out_extenddata <= in_extenddata; 130 out_extenddata <= in_extenddata;
43 - out_PC_4 <= out_PC_4; 131 + out_PC_4 <= in_PC_4;
44 out_tempPCjump <= in_tempPCjump; 132 out_tempPCjump <= in_tempPCjump;
45 - out_readreg_num1 <= in_readreg_num1; 133 + end
46 - out_readreg_num2 <= in_readreg_num2;
47 end 134 end
135 +always @(negedge stall) begin
136 + stallfinished = 1'b1;
137 +end
138 +
48 endmodule 139 endmodule
49 140
50 141
...@@ -53,6 +144,7 @@ module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_mem ...@@ -53,6 +144,7 @@ module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_mem
53 out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 144 out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump,
54 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch); 145 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
55 input clk; 146 input clk;
147 +
56 input[4:0] in_writereg_num; 148 input[4:0] in_writereg_num;
57 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump; 149 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
58 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch; 150 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
...@@ -79,8 +171,9 @@ endmodule ...@@ -79,8 +171,9 @@ endmodule
79 171
80 172
81 module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 173 module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump,
82 - out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCbranch, out_PCjump); 174 + out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCjump, out_PCbranch);
83 input clk; 175 input clk;
176 +
84 input[4:0] in_writereg_num; 177 input[4:0] in_writereg_num;
85 input in_regwrite, in_memtoreg, in_jump; 178 input in_regwrite, in_memtoreg, in_jump;
86 input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump; 179 input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
...@@ -96,31 +189,33 @@ always @(posedge clk) begin ...@@ -96,31 +189,33 @@ always @(posedge clk) begin
96 189
97 out_aluresult <= in_aluresult; 190 out_aluresult <= in_aluresult;
98 out_memreaddata <= in_memreaddata; 191 out_memreaddata <= in_memreaddata;
99 - out_PCbranch <= out_PCbranch; 192 + out_PCjump <= in_PCjump;
100 - out_PCjump <= out_PCjump; 193 + out_PCbranch <= in_PCbranch;
101 end 194 end
102 endmodule 195 endmodule
103 196
104 /* Not Finished */ 197 /* Not Finished */
105 -module PCcounter(clk, in_pc, out_nextpc); 198 +module PCcounter(clk, stall, in_pc, out_nextpc);
106 -input clk; 199 +input clk, stall;
200 +
107 input[31:0] in_pc; 201 input[31:0] in_pc;
108 output reg[31:0] out_nextpc; 202 output reg[31:0] out_nextpc;
203 +
109 reg[31:0] PC; 204 reg[31:0] PC;
205 +reg stallfinished;
110 206
111 initial begin 207 initial begin
112 PC = 32'h00000000; 208 PC = 32'h00000000;
209 + stallfinished = 1'b1;
113 end 210 end
114 211
115 always @(posedge clk) begin 212 always @(posedge clk) begin
116 -/*
117 - case(in_pc[31]) // if in_pc is available, PC = in_pc.
118 - 1'b0: PC = in_pc;
119 - 1'b1: PC = in_pc;
120 - endcase
121 -*/
122 - PC <= PC+4;
123 - out_nextpc <= PC;
124 -end
125 213
214 + if(stallfinished == 1'b1) stallfinished = 1'b0;
215 + else if(stall == 1'b0) PC = PC+4;
216 + out_nextpc = PC;
217 +end
218 +always @(negedge stall) begin
219 + stallfinished = 1'b1;
220 +end
126 endmodule 221 endmodule
......
1 module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2); 1 module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
2 -
3 input clk; 2 input clk;
4 input[4:0] readin1, readin2, writein; 3 input[4:0] readin1, readin2, writein;
5 input[31:0] writedata; 4 input[31:0] writedata;
......
1 module ShiftLeft2(shiftinput, shiftoutput); 1 module ShiftLeft2(shiftinput, shiftoutput);
2 -
3 input[31:0] shiftinput; 2 input[31:0] shiftinput;
4 output[31:0] shiftoutput; 3 output[31:0] shiftoutput;
5 4
......
1 module SignExtend(signedinput, signedoutput); 1 module SignExtend(signedinput, signedoutput);
2 -
3 input[15:0] signedinput; 2 input[15:0] signedinput;
4 output[31:0] signedoutput; 3 output[31:0] signedoutput;
5 4
......
1 +module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite,
2 + in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
3 + out_stallsignal);
4 +input clk;
5 +input in_ex_regwrite, in_mem_regwrite, in_wb_regwrite;
6 +input[4:0] in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
7 +output reg out_stallsignal;
8 +
9 +initial out_stallsignal = 1'b0;
10 +
11 +always @(negedge clk) begin
12 + if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_readreg_num1 || in_ex_writereg_num==in_readreg_num2)) begin
13 + out_stallsignal = 1'b1;
14 + end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_readreg_num1 || in_mem_writereg_num==in_readreg_num2)) begin
15 + out_stallsignal = 1'b1;
16 + end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_readreg_num1 || in_wb_writereg_num==in_readreg_num2)) begin
17 + out_stallsignal = 1'b1;
18 + end else out_stallsignal = 1'b0;
19 +end
20 +
21 +endmodule
22 +
23 +
1 module test; 1 module test;
2 +wire clk;
3 +wire stall;
4 +wire[4:0] in1, out1, out2, out3, out4, out5, out6;
5 +wire stall_1;
6 +
7 +assign stall_1 = 0;
8 +
9 +Clock clock(clk);
10 +testPC tpc(clk, stall, in1);
11 +testA ta1(clk, stall, in1, out1);
12 +testA ta2(clk, stall, out1, out2);
13 +testA ta3(clk, stall, out2, out3);
14 +testA ta4(clk, stall_1, out3, out4);
15 +testA ta5(clk, stall_1, out4, out5);
16 +testA ta6(clk, stall_1, out5, out6);
17 +testB stl(clk, out1, stall);
18 +
19 +initial begin
20 +end
21 +endmodule
22 +
23 +
24 +module testA(clk, stall, in1, out1);
25 +input clk, stall;
26 +input[4:0] in1;
27 +output reg[4:0] out1;
28 +
29 +reg[4:0] temp1;
30 +reg stallfinished;
31 +
32 +initial begin
33 + temp1 = 5'b00000;
34 + out1 = 5'b00000;
35 + stallfinished = 1'b0;
36 +end
37 +
38 +always @(posedge clk) begin
39 + if(stall == 1'b1) out1 <= 5'b00000;
40 + else if(stallfinished == 1'b1) begin
41 + out1 <= temp1;
42 + stallfinished <= 1'b0;
43 + end
44 + else out1 <= in1;
45 +end
46 +always @(posedge stall) begin
47 + temp1 = in1;
48 +end
49 +always @(negedge stall) begin
50 + stallfinished = 1'b1;
51 +end
52 +endmodule
53 +
54 +
55 +module testB(clk, out1, stall);
56 +input clk;
57 +input[4:0] out1;
58 +output reg stall;
59 +
60 +integer i;
61 +
62 +initial begin
63 + stall = 1'b0;
64 + i = 0;
65 +end
66 +
67 +always @(negedge clk)
68 + if(i > 0) i = i-1;
69 + else begin
70 + if(out1 == 5'b00101) begin
71 + i = 2;
72 + stall = 1'b1;
73 + end
74 + else stall = 1'b0;
75 + end
76 +endmodule
77 +
78 +
79 +module testPC(clk, stall, in1);
80 +input clk, stall;
81 +output reg[4:0] in1;
82 +
83 +reg[4:0] PC;
84 +
85 +initial begin
86 + PC = 5'd0;
87 +end
88 +always @(posedge clk) begin
89 + if(stall == 1'b0) PC <= PC+1;
90 + in1 <= PC;
91 +end
92 +endmodule
93 +
94 +/*
95 +module test;
2 96
3 wire clk; 97 wire clk;
4 reg sig1; 98 reg sig1;
...@@ -22,22 +116,6 @@ initial begin ...@@ -22,22 +116,6 @@ initial begin
22 #100; 116 #100;
23 end 117 end
24 118
25 -/*
26 -wire clk;
27 -reg[31:0] pc;
28 -wire[31:0] instr, tempPC;
29 -
30 -Clock clock(clk);
31 -InstructionFetch IF(clk, pc, instr, tempPC);
32 -
33 -initial begin
34 - pc = 32'hfffffffc;
35 -end
36 -
37 -always @(negedge clk) begin
38 - pc = pc + 4;
39 -end
40 -*/
41 endmodule 119 endmodule
42 120
43 module testA(clk, sig1, in1, out1, out2); 121 module testA(clk, sig1, in1, out1, out2);
...@@ -52,3 +130,4 @@ always @(posedge clk) begin ...@@ -52,3 +130,4 @@ always @(posedge clk) begin
52 end 130 end
53 131
54 endmodule 132 endmodule
133 +*/
...\ No newline at end of file ...\ No newline at end of file
......
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