module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 
	in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 
	out_stallsignal);
input clk;
input in_ex_regwrite, in_mem_regwrite, in_wb_regwrite;
input[4:0] in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
output reg out_stallsignal;

initial out_stallsignal = 1'b0;

always @(negedge clk) begin
	if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_readreg_num1 || in_ex_writereg_num==in_readreg_num2)) begin
		out_stallsignal = 1'b1;
	end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_readreg_num1 || in_mem_writereg_num==in_readreg_num2)) begin
		out_stallsignal = 1'b1;
	end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_readreg_num1 || in_wb_writereg_num==in_readreg_num2)) begin
		out_stallsignal = 1'b1;	
	end else out_stallsignal = 1'b0;
end

endmodule