module InstructionMemory(address, instruction);

input[31:0] address;
output reg[31:0] instruction;

reg[31:0] instr_mem[127:0];

initial begin
instr_mem[0] = 32'd0;
instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
instr_mem[2] = 32'd0;
instr_mem[3] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
instr_mem[4] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
instr_mem[5] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
instr_mem[6] = 32'b00100100000011010000000000000011;		// addi, $0 $13 3
instr_mem[7] = 32'b00100100000010010000000000000001;		// addi, $0 $9 1
instr_mem[8] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
instr_mem[9] = 32'd0;
end
/*
initial begin
out_clk = 1'b0;

instr_mem[0] = 32'd0;
instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
instr_mem[3] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
instr_mem[4] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
instr_mem[5] = 32'b00010001000010100000000000000001;		// beq, $8 $10 +1
instr_mem[6] = 32'd0;
instr_mem[7] = 32'b00000001000010010000000000011000;		// mult, $8 $9
instr_mem[8] = 32'd0;
instr_mem[9] = 32'b00000000000000000110000000010000;		// mfhi, $12
instr_mem[10] = 32'b00000000000000000110100000010010;		// mflo, $13
instr_mem[11] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
instr_mem[12] = 32'd0;
instr_mem[13] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
instr_mem[14] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
instr_mem[15] = 32'd0;
instr_mem[16] = 32'b00000000000000000000000000001000;		// jr, $0
end
*/
always @ (*) begin
	instruction = instr_mem[address/4];
end

endmodule