module IF_ID(clk, stall, in_instruction, in_PC_4, 
	out_instruction, out_PC_4);
input clk, stall;

input[31:0] in_instruction, in_PC_4;

output reg[31:0] out_instruction, out_PC_4;

reg[31:0] temp_instruction, temp_PC_4;

reg stallfinished;

initial begin
	stallfinished = 1'b0;
end

always @(posedge clk) begin

	if(stall == 1'b1) begin
		out_instruction <= 32'h00000000;
		out_PC_4 <= 32'h00000000;
	end
	else if(stallfinished == 1'b1) begin
		out_instruction <= temp_instruction;
		out_PC_4 <= temp_PC_4;
		
		stallfinished = 1'b0;
	end
	else begin
		out_instruction <= in_instruction;
		out_PC_4 <= in_PC_4;
	end
end

always @(posedge stall) begin
	temp_instruction <= out_instruction;
	temp_PC_4 <= out_PC_4;
end
always @(negedge stall) begin
	stallfinished = 1'b1;
end
endmodule


module ID_EX(clk, stall, in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 
	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, 
	out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 
	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
input clk, stall;

input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg;
input[3:0] in_aluctrl;
input[2:0] in_branch;
input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump;

output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2;
output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg;
output reg[3:0] out_aluctrl;
output reg[2:0] out_branch;
output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;

reg stallfinished;

initial begin
	stallfinished = 1'b0;
end
always @(posedge clk) begin
	if(stall == 1'b1) begin
		out_writereg_num <= 5'b00000;
		out_readreg_num1 <= 5'b00000;
		out_readreg_num2 <= 5'b00000;

		out_regwrite <= 1'b0;
		out_alusrc <= 1'b0;
		out_aluctrl <= 4'b0000;
		out_memread <= 1'b0;
		out_memwrite <= 1'b0;
		out_memtoreg <= 1'b0;
		out_branch <= 3'b000;
		out_jump <= 1'b0;
		out_jumpreg <= 1'b0;

		out_readdata1 <= 32'h00000000;
		out_readdata2 <= 32'h00000000;
		out_extenddata <= 32'h00000000;
		out_PC_4 <= 32'h00000000;
		out_tempPCjump <= 32'h00000000;
	end 
	else if(stallfinished == 1'b1) begin
		out_writereg_num <= 5'b00000;
		out_readreg_num1 <= 5'b00000;
		out_readreg_num2 <= 5'b00000;

		out_regwrite <= 1'b0;
		out_alusrc <= 1'b0;
		out_aluctrl <= 4'b0000;
		out_memread <= 1'b0;
		out_memwrite <= 1'b0;
		out_memtoreg <= 1'b0;
		out_branch <= 3'b000;
		out_jump <= 1'b0;
		out_jumpreg <= 1'b0;

		out_readdata1 <= 32'h00000000;
		out_readdata2 <= 32'h00000000;
		out_extenddata <= 32'h00000000;
		out_PC_4 <= 32'h00000000;
		out_tempPCjump <= 32'h00000000;
		
		stallfinished = 1'b0;
	end 
	else begin
		out_writereg_num <= in_writereg_num;
		out_readreg_num1 <= in_readreg_num1;
		out_readreg_num2 <= in_readreg_num2;

		out_regwrite <= in_regwrite;
		out_alusrc <= in_alusrc;
		out_aluctrl <= in_aluctrl;
		out_memread <= in_memread;
		out_memwrite <= in_memwrite;
		out_memtoreg <= in_memtoreg;
		out_branch <= in_branch;
		out_jump <= in_jump;
		out_jumpreg <= in_jumpreg;

		out_readdata1 <= in_readdata1;
		out_readdata2 <= in_readdata2;
		out_extenddata <= in_extenddata;
		out_PC_4 <= in_PC_4;
		out_tempPCjump <= in_tempPCjump;
	end
end
always @(negedge stall) begin
	stallfinished = 1'b1;
end

endmodule


module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, 
	in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 
	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 
	out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
input clk;

input[4:0] in_writereg_num;
input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
output reg[4:0] out_writereg_num;
output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump;
output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;

always @(posedge clk) begin
	out_writereg_num <= in_writereg_num;
	out_regwrite <= in_regwrite;
	out_memread <= in_memread;
	out_memwrite <= in_memwrite;
	out_memtoreg <= in_memtoreg;
	out_branch <= in_branch;
	out_jump <= in_jump;

	out_aluresult <= in_aluresult;
	out_mem_writedata <= in_mem_writedata;
	out_PC_4 <= in_PC_4;
	out_PCjump <= in_PCjump;
	out_tempPCbranch <= in_tempPCbranch;
end
endmodule


module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 
	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCjump, out_PCbranch);
input clk;

input[4:0] in_writereg_num;
input in_regwrite, in_memtoreg, in_jump;
input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
output reg[4:0] out_writereg_num;
output reg out_regwrite, out_memtoreg, out_jump;
output reg[31:0] out_aluresult, out_memreaddata, out_PCbranch, out_PCjump;

always @(posedge clk) begin
	out_writereg_num <= in_writereg_num;
	out_regwrite <= in_regwrite;
	out_memtoreg <= in_memtoreg;
	out_jump <= in_jump;

	out_aluresult <= in_aluresult;
	out_memreaddata <= in_memreaddata;
	out_PCjump <= in_PCjump;
	out_PCbranch <= in_PCbranch;
end
endmodule

/* Not Finished */
module PCcounter(clk, stall, in_pc, out_nextpc);
input clk, stall;

input[31:0] in_pc;
output reg[31:0] out_nextpc;

reg[31:0] PC;
reg stallfinished;

initial begin
	PC = 32'h00000000;
	stallfinished = 1'b1;
end

always @(posedge clk) begin
	
	if(stallfinished == 1'b1) stallfinished = 1'b0;
	else if(stall == 1'b0) PC = PC+4;
	out_nextpc = PC;
end
always @(negedge stall) begin
	stallfinished = 1'b1;
end
endmodule