오타 수정 및 stall 기능 추가(data hazard)

 module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch);
-
 input clk;
 input[31:0] aluin1, aluin2;
 input[3:0] aluctrl;
 output reg[31:0] aluout;
-// output alubranch;
 output reg[5:0] alubranch;
 
 reg overflow;
 reg[63:0] temp;
-reg[31:0] HI, LO;				// HI, LO register for multiplication and division.
-reg[31:0] tempHI, tempLO;			// temporary HI, LO register for multiplication and division.
-
-// assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
+reg[31:0] HI, LO;					// HI, LO register for multiplication and division.
+reg[31:0] tempHI, tempLO;				// temporary HI, LO register for multiplication and division.
 
 initial begin
 	temp = 64'h0000000000000000;
@@ -23,44 +19,45 @@ initial begin
 end
 
 always @(*) begin
-overflow = 0;
-case(aluctrl)
-	4'b0000: aluout <= aluin1 & aluin2;	// and
-	4'b0001: aluout <= aluin1 | aluin2;	// or
-	4'b0010: begin 				// add
-		aluout = aluin1 + aluin2;
-		overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0;	// overflow detection.
-	end
-	4'b0110: begin				// sub
-		aluout = aluin1 - aluin2;
-		overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0;	// overflow detection.
-		alubranch[0] = (aluout == 32'd0) ? 1'b1 : 1'b0;	// beq
-		alubranch[1] = (aluout != 32'd0) ? 1'b1 : 1'b0;	// bne
-		alubranch[2] = (aluin1 > 32'd0) ? 1'b1 : 1'b0;	// bgtz 
-		alubranch[3] = (aluin1 < 32'd0) ? 1'b1 : 1'b0;	// bltz
-		alubranch[4] = (aluin1 >= 32'd0) ? 1'b1 : 1'b0;	// bgez 
-		alubranch[5] = (aluin1 <= 32'd0) ? 1'b1 : 1'b0;	// blez
-	end
+	overflow = 1'b0;
+	alubranch = 6'b0;
+	case(aluctrl)
+		4'b0000: aluout <= aluin1 & aluin2;	// and
+		4'b0001: aluout <= aluin1 | aluin2;	// or
+		4'b0010: begin 				// add
+			aluout = aluin1 + aluin2;
+			overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0;	// overflow detection.
+		end
+		4'b0110: begin				// sub
+			aluout = aluin1 - aluin2;
+			overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0;	// overflow detection.
+			alubranch[0] = (aluout == 32'h00000000) ? 1'b1 : 1'b0;	// beq
+			alubranch[1] = (aluout != 32'h00000000) ? 1'b1 : 1'b0;	// bne
+			alubranch[2] = (aluin1 > 32'h00000000) ? 1'b1 : 1'b0;	// bgtz 
+			alubranch[3] = (aluin1 < 32'h00000000) ? 1'b1 : 1'b0;	// bltz
+			alubranch[4] = (aluin1 >= 32'h00000000) ? 1'b1 : 1'b0;	// bgez 
+			alubranch[5] = (aluin1 <= 32'h00000000) ? 1'b1 : 1'b0;	// blez
+		end
 
-	4'b0111: begin				// slt
-		aluout[31:1] = {31{1'b0}};
-		aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0;
-	end
-	4'b1000: begin				// mult
-		temp = aluin1 * aluin2;
-		tempHI <= temp[63:32];
-		tempLO <= temp[31:0];
-	end
-	4'b1001: begin				// div
-		tempHI <= aluin1 % aluin2;
-		tempLO <= aluin1 / aluin2;
-	end
-	4'b1010: aluout <= HI;			// mfhi
-	4'b1011: aluout <= LO;			// mflo
-	4'b1100: aluout <= ~(aluin1 | aluin2);	// nor
-	4'b1101: aluout <= aluin1 ^ aluin2;	// xor
-	default: aluout <= 32'b0;
-endcase
+		4'b0111: begin				// slt
+			aluout[31:1] = {31{1'b0}};
+			aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0;
+		end
+		4'b1000: begin				// mult
+			temp = aluin1 * aluin2;
+			tempHI <= temp[63:32];
+			tempLO <= temp[31:0];
+		end
+		4'b1001: begin				// div
+			tempHI <= aluin1 % aluin2;
+			tempLO <= aluin1 / aluin2;
+		end
+		4'b1010: aluout <= HI;			// mfhi
+		4'b1011: aluout <= LO;			// mflo
+		4'b1100: aluout <= ~(aluin1 | aluin2);	// nor
+		4'b1101: aluout <= aluin1 ^ aluin2;	// xor
+		default: aluout <= 32'h00000000;
+	endcase
 end
 
 always @(negedge clk) begin

 module Adder(adderinput1, adderinput2, adderoutput);
-
 input[31:0] adderinput1, adderinput2;
 output[31:0] adderoutput;
 

 module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
-
 input[5:0] opcode;
 input[4:0] rt;
 input[5:0] funct;

 module DataMemory(clk, address, writedata, memread, memwrite, readdata);
-
 input clk;
 input[31:0] address, writedata;
 input memread, memwrite;
-output[31:0] readdata;
+output reg[31:0] readdata;
 
+integer i;
 reg[31:0] mem[255:0];
 
-assign readdata = memread ? mem[address/4] : 32'd0;
+initial begin
+	for(i=0; i<256; i=i+1) mem[i] = 32'd0;
+end
 
 always @(negedge clk) begin
+	if(memread== 1'b1) begin
+		readdata = mem[address/4];
+	end
 	if(memwrite==1'b1) begin
 		mem[address/4] = writedata;
 	end

-/* Not Finished */
-module Stall(clk, in_readreg_num1, in_readreg_num2, in_writereg_num);
-
-input clk;
-input[4:0] in_readreg_num1, in_readreg_num2, in_writereg_num;
-
-reg[4:0] writeregs;
-
-endmodule
-
-

@@ -7,24 +7,39 @@ reg[31:0] instr_mem[127:0];
 
 initial begin
 instr_mem[0] = 32'd0;
-instr_mem[1] = 32'b00100100000010000000000011111111;		// addi, $0 $8 255
-instr_mem[2] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
-instr_mem[3] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
-instr_mem[4] = 32'b00010001000010100000000000000001;		// beq, $8 $10 +1
-instr_mem[5] = 32'd0;
-instr_mem[6] = 32'b00000001000010010000000000011000;		// mult, $8 $9
-instr_mem[7] = 32'd0;
-instr_mem[8] = 32'b00000000000000000110000000010000;		// mfhi, $12
-instr_mem[9] = 32'b00000000000000000110100000010010;		// mflo, $13
-instr_mem[10] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
-instr_mem[11] = 32'd0;
-instr_mem[12] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
-instr_mem[13] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
-instr_mem[14] = 32'd0;
-instr_mem[15] = 32'b00000000000000000000000000001000;		// jr, $0
-
+instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[2] = 32'd0;
+instr_mem[3] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[4] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[5] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[6] = 32'b00100100000011010000000000000011;		// addi, $0 $13 3
+instr_mem[7] = 32'b00100100000010010000000000000001;		// addi, $0 $9 1
+instr_mem[8] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
+instr_mem[9] = 32'd0;
 end
+/*
+initial begin
+out_clk = 1'b0;
 
+instr_mem[0] = 32'd0;
+instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[3] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
+instr_mem[4] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
+instr_mem[5] = 32'b00010001000010100000000000000001;		// beq, $8 $10 +1
+instr_mem[6] = 32'd0;
+instr_mem[7] = 32'b00000001000010010000000000011000;		// mult, $8 $9
+instr_mem[8] = 32'd0;
+instr_mem[9] = 32'b00000000000000000110000000010000;		// mfhi, $12
+instr_mem[10] = 32'b00000000000000000110100000010010;		// mflo, $13
+instr_mem[11] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
+instr_mem[12] = 32'd0;
+instr_mem[13] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
+instr_mem[14] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
+instr_mem[15] = 32'd0;
+instr_mem[16] = 32'b00000000000000000000000000001000;		// jr, $0
+end
+*/
 always @ (*) begin
 	instruction = instr_mem[address/4];
 end

-D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
+D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module testbench
+-- Compiling module test
+-- Compiling module testA
+-- Compiling module testB
+-- Compiling module testPC
 
 Top level modules:
-	testbench
+	test
 
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module test
--- Compiling module testA
+-- Compiling module testbench
 
 Top level modules:
-	test
+	testbench
 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
@@ -41,6 +43,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7
 Top level modules:
 	Register
 
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module MIPS_Pipeline
+
+Top level modules:
+	MIPS_Pipeline
+
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module IF_ID
@@ -56,14 +65,7 @@ Top level modules:
 	MEM_WB
 	PCcounter
 
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module MIPS_Pipeline
-
-Top level modules:
-	MIPS_Pipeline
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Stall
 
@@ -84,6 +86,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7
 Top level modules:
 	Control
 
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module ALU
+
+Top level modules:
+	ALU
+
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Mux5bit
@@ -95,12 +104,12 @@ Top level modules:
 	Mux32bit
 	MuxBranchSignal
 
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module ALU
+-- Compiling module ShiftLeft2
 
 Top level modules:
-	ALU
+	ShiftLeft2
 
 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
@@ -109,14 +118,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7
 Top level modules:
 	DataMemory
 
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module ShiftLeft2
-
-Top level modules:
-	ShiftLeft2
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Clock
 

@@ -816,7 +816,7 @@ Resolution = ns
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 100
+RunLength = 100 ns
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 10000000
@@ -2035,38 +2035,38 @@ Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 16
-Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590428983 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590335687 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591501317 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1590428983 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039528 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757617 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591531598 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757768 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1591579676 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452599 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757593 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1591621120 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590758341 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1590758365 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591621089 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591618522 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039196 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757464 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590755668 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590755442 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_15 = D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452194 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452276 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452448 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039219 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452257 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591110854 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0

 // Test Required
 module MIPS_Pipeline;
 
-wire clk;							// clock
+wire clk;
+wire stallsignal;
 wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		
 
 wire[31:0] instr;						// loaded instruction.
@@ -46,14 +47,21 @@ wire memwb_regwrite, memwb_memtoreg, memwb_jump;
 wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;
 
 
+
+wire tempstall;
+assign tempstall = 1'b0;
+
 Clock clock(clk);
-PCcounter pccounter(clk, nextPC, instr_address);
+PCcounter pccounter(clk, stallsignal, nextPC, instr_address);
+Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, 
+	ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,  
+	stallsignal);
 
 // Instruction Fetch
 InstructionMemory instrmem(instr_address, instr);
-Adder add_pc4(PC, 32'h00000004, addPC4);
+Adder add_pc4(instr_address, 32'h00000004, addPC4);
 
-IF_ID ifid(clk, instr, addPC4, 
+IF_ID ifid(clk, stallsignal, instr, addPC4, 
 	ifid_instr, ifid_PC_4);
 
 // Instruction Decode
@@ -63,15 +71,15 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re
 SignExtend extend(ifid_instr[15:0], extend_output);
 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
 
-ID_EX idex(clk, reg_writereg1, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 
-	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, ifid_instr[25:21], ifid_instr[20:16], 
-	idex_writereg1, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 
-	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump, idex_readreg_num1, idex_readreg_num2);
+ID_EX idex(clk, stallsignal, reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 
+	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, 
+	idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 
+	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
 
 // Execute
-Mux32bit mux_alusrc(idex_readdata2, idex_extend,  idex_alusrc,  alu_input2);
+Mux32bit mux_alusrc(idex_readdata2, idex_extenddata,  idex_alusrc,  alu_input2);
 ALU alu(clk, idex_readdata1, alu_input2,  idex_aluctrl,  alu_result, alu_branch);
-ShiftLeft2 shiftBranch(idex_extend, shiftBranch_output);
+ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
 Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
 MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);
@@ -86,80 +94,16 @@ DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exm
 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch,  exmem_branch ,  tempPC_branch);
 
 MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 
-	exmem_aluresult, mem_readdata, tempPC_branch, exmem_PCjump, 
+	exmem_aluresult, mem_readdata, exmem_PCjump, tempPC_branch, 
 	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 
-	memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump);
+	memwb_aluresult, memwb_memreaddata, memwb_PCjump, memwb_PCbranch);
 
 // Writeback
 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  reg_writedata);
 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump,  memwb_jump,  nextPC);
 
 
-
-
-always @(posedge clk) begin
-
-end
-
-/*
-wire clk;							// clock
-reg[31:0] PC, instr_address;
-
-// IF - ID
-wire[31:0] if_id_instruction, if_id_pc_4;
-
-// ID - EX
-wire[31:0] id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump;
-wire[4:0] id_ex_writereg, id_hh_readreg1, id_hh_readreg2;
-wire id_ex_regwrite, id_ex_alusrc, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg;
-wire[3:0] id_ex_aluctrl;
-
-// EX - MEM
-wire[31:0] ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch;
-wire[4:0] ex_mem_writereg;
-wire ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump;
-
-// MEM - WB
-wire[4:0] mem_wb_writereg_num;
-wire mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump;
-wire[31:0] mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump;
-
-// WB - etc.
-wire wb_id_regwrite;
-wire[4:0] wb_id_writereg;
-wire[31:0] wb_id_reg_writedata;
-wire[31:0] wb_nextPC;
-
-Clock clock(clk);
-
-InstructionFetch IF(clk, PC,  if_id_instruction, if_id_pc_4);
-
-InstructionDecode ID(clk, if_id_instruction, if_id_pc_4, wb_id_writereg, wb_id_reg_writedata, wb_id_regwrite, 
-	id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
-	id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump);
-
-Execute EX(clk, id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
-	id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump, 
-	ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump, 
-	ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch);
-
-Mem MEM(clk, ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump, 
-	ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch, 
-	mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump);
-
-WriteBack WB(clk, mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump, 
-	wb_id_regwrite, wb_id_writereg, wb_id_reg_writedata, wb_nextPC);
-
-initial begin
-	PC = 32'hfffffffc;
-end
-
 always @(posedge clk) begin
-	instr_address = PC;
 end
 
-always @(negedge clk) begin
-	PC = PC + 4;
-end
-*/
 endmodule

 module MIPS_SingleCycle;
 
-wire clk;							// clock
-reg[31:0] PC;							// program counter
+wire clk;								// clock
+reg[31:0] PC;								// program counter
 reg[31:0] instr_address;
 wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		
 
-wire[31:0] instr;						// loaded instruction.
+wire[31:0] instr;							// loaded instruction.
 
-wire[4:0] reg_writereg1;					// register number for the write data.
-wire[31:0] reg_writedata;					// data that will be written in the register.
-wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.
+wire[4:0] reg_writereg1;						// register number for the write data.
+wire[31:0] reg_writedata;						// data that will be written in the register.
+wire[31:0] reg_readdata1, reg_readdata2;				// data from the requested register.
 
-wire[31:0] alu_input2;						// input data of ALU.
-wire[31:0] alu_result;						// result data of ALU.
-wire[5:0] alu_branch;						// indicator for branch operation.
+wire[31:0] alu_input2;							// input data of ALU.
+wire[31:0] alu_result;							// result data of ALU.
+wire[5:0] alu_branch;							// indicator for branch operation.
 
-wire[31:0] mem_readdata;					// data from the requested address.
+wire[31:0] mem_readdata;						// data from the requested address.
 
 wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
 wire[3:0] ctrl_aluctrl;
-wire[2:0] ctrl_branch;						// control signals.
+wire[2:0] ctrl_branch;							// control signals.
 
 wire[31:0] extend_output;
 
 wire[31:0] shiftBranch_output;
 wire[31:0] shiftJump_output;
 
+
 Clock clock(clk);
 InstructionMemory instrmem(instr_address, instr);
 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata,  ctrl_regwrite,  reg_readdata1, reg_readdata2);
 ALU alu(clk, reg_readdata1, alu_input2,  ctrl_aluctrl,  alu_result, alu_branch);
 DataMemory datamem(clk, alu_result, reg_readdata2,  ctrl_memread, ctrl_memwrite,  mem_readdata);
 Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
+
 Mux5bit mux_regdst(instr[20:16], instr[15:11],  ctrl_regdst,  reg_writereg1);
 MuxBranchSignal mux_branchsignal(alu_branch,  ctrl_branch,  branch_signal);
 Mux32bit mux_alusrc(reg_readdata2, extend_output,  ctrl_alusrc,  alu_input2);

@@ -44,3 +44,4 @@ always @(*) begin
 end
 
 endmodule
+

-module IF_ID(clk, in_instruction, in_PC_4, 
+module IF_ID(clk, stall, in_instruction, in_PC_4, 
 	out_instruction, out_PC_4);
-input clk;
+input clk, stall;
+
 input[31:0] in_instruction, in_PC_4;
+
 output reg[31:0] out_instruction, out_PC_4;
 
+reg[31:0] temp_instruction, temp_PC_4;
+
+reg stallfinished;
+
+initial begin
+	stallfinished = 1'b0;
+end
+
 always @(posedge clk) begin
-	out_instruction <= in_instruction;
-	out_PC_4 <= in_PC_4;
+
+	if(stall == 1'b1) begin
+		out_instruction <= 32'h00000000;
+		out_PC_4 <= 32'h00000000;
+	end
+	else if(stallfinished == 1'b1) begin
+		out_instruction <= temp_instruction;
+		out_PC_4 <= temp_PC_4;
+		
+		stallfinished = 1'b0;
+	end
+	else begin
+		out_instruction <= in_instruction;
+		out_PC_4 <= in_PC_4;
+	end
+end
+
+always @(posedge stall) begin
+	temp_instruction <= out_instruction;
+	temp_PC_4 <= out_PC_4;
+end
+always @(negedge stall) begin
+	stallfinished = 1'b1;
 end
 endmodule
 
 
-module ID_EX(clk, in_writereg_num, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 
-	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2, 
-	out_writereg_num, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 
-	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2);
-input clk;
-input[4:0] in_writereg_num;
-input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg;
+module ID_EX(clk, stall, in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 
+	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, 
+	out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 
+	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
+input clk, stall;
+
+input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
+input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg;
 input[3:0] in_aluctrl;
-input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2;
-output reg[4:0] out_writereg_num;
-output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg;
+input[2:0] in_branch;
+input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump;
+
+output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2;
+output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg;
 output reg[3:0] out_aluctrl;
-output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2;
+output reg[2:0] out_branch;
+output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
+
+reg stallfinished;
 
+initial begin
+	stallfinished = 1'b0;
+end
 always @(posedge clk) begin
-	out_writereg_num <= in_writereg_num;
-	out_regwrite <= in_regwrite;
-	out_alusrc <= in_alusrc;
-	out_aluctrl <= in_aluctrl;
-	out_memread <= in_memread;
-	out_memwrite <= in_memwrite;
-	out_memtoreg <= in_memtoreg;
-	out_branch <= in_branch;
-	out_jump <= in_jump;
-	out_jumpreg <= in_jumpreg;
-
-	out_readdata1 <= in_readdata1;
-	out_readdata2 <= in_readdata2;
-	out_extenddata <= in_extenddata;
-	out_PC_4 <= out_PC_4;
-	out_tempPCjump <= in_tempPCjump;
-	out_readreg_num1 <= in_readreg_num1;
-	out_readreg_num2 <= in_readreg_num2;
+	if(stall == 1'b1) begin
+		out_writereg_num <= 5'b00000;
+		out_readreg_num1 <= 5'b00000;
+		out_readreg_num2 <= 5'b00000;
+
+		out_regwrite <= 1'b0;
+		out_alusrc <= 1'b0;
+		out_aluctrl <= 4'b0000;
+		out_memread <= 1'b0;
+		out_memwrite <= 1'b0;
+		out_memtoreg <= 1'b0;
+		out_branch <= 3'b000;
+		out_jump <= 1'b0;
+		out_jumpreg <= 1'b0;
+
+		out_readdata1 <= 32'h00000000;
+		out_readdata2 <= 32'h00000000;
+		out_extenddata <= 32'h00000000;
+		out_PC_4 <= 32'h00000000;
+		out_tempPCjump <= 32'h00000000;
+	end 
+	else if(stallfinished == 1'b1) begin
+		out_writereg_num <= 5'b00000;
+		out_readreg_num1 <= 5'b00000;
+		out_readreg_num2 <= 5'b00000;
+
+		out_regwrite <= 1'b0;
+		out_alusrc <= 1'b0;
+		out_aluctrl <= 4'b0000;
+		out_memread <= 1'b0;
+		out_memwrite <= 1'b0;
+		out_memtoreg <= 1'b0;
+		out_branch <= 3'b000;
+		out_jump <= 1'b0;
+		out_jumpreg <= 1'b0;
+
+		out_readdata1 <= 32'h00000000;
+		out_readdata2 <= 32'h00000000;
+		out_extenddata <= 32'h00000000;
+		out_PC_4 <= 32'h00000000;
+		out_tempPCjump <= 32'h00000000;
+		
+		stallfinished = 1'b0;
+	end 
+	else begin
+		out_writereg_num <= in_writereg_num;
+		out_readreg_num1 <= in_readreg_num1;
+		out_readreg_num2 <= in_readreg_num2;
+
+		out_regwrite <= in_regwrite;
+		out_alusrc <= in_alusrc;
+		out_aluctrl <= in_aluctrl;
+		out_memread <= in_memread;
+		out_memwrite <= in_memwrite;
+		out_memtoreg <= in_memtoreg;
+		out_branch <= in_branch;
+		out_jump <= in_jump;
+		out_jumpreg <= in_jumpreg;
+
+		out_readdata1 <= in_readdata1;
+		out_readdata2 <= in_readdata2;
+		out_extenddata <= in_extenddata;
+		out_PC_4 <= in_PC_4;
+		out_tempPCjump <= in_tempPCjump;
+	end
+end
+always @(negedge stall) begin
+	stallfinished = 1'b1;
 end
+
 endmodule
 
 
@@ -53,6 +144,7 @@ module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_mem
 	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 
 	out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
 input clk;
+
 input[4:0] in_writereg_num;
 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
@@ -79,8 +171,9 @@ endmodule
 
 
 module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 
-	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCbranch, out_PCjump);
+	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCjump, out_PCbranch);
 input clk;
+
 input[4:0] in_writereg_num;
 input in_regwrite, in_memtoreg, in_jump;
 input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
@@ -96,31 +189,33 @@ always @(posedge clk) begin
 
 	out_aluresult <= in_aluresult;
 	out_memreaddata <= in_memreaddata;
-	out_PCbranch <= out_PCbranch;
-	out_PCjump <= out_PCjump;
+	out_PCjump <= in_PCjump;
+	out_PCbranch <= in_PCbranch;
 end
 endmodule
 
 /* Not Finished */
-module PCcounter(clk, in_pc, out_nextpc);
-input clk;
+module PCcounter(clk, stall, in_pc, out_nextpc);
+input clk, stall;
+
 input[31:0] in_pc;
 output reg[31:0] out_nextpc;
+
 reg[31:0] PC;
+reg stallfinished;
 
 initial begin
 	PC = 32'h00000000;
+	stallfinished = 1'b1;
 end
 
 always @(posedge clk) begin
-/*
-	case(in_pc[31])					// if in_pc is available, PC = in_pc.
-		1'b0: PC = in_pc;
-		1'b1: PC = in_pc;
-	endcase
-*/
-	PC <= PC+4;
-	out_nextpc <= PC;
+	
+	if(stallfinished == 1'b1) stallfinished = 1'b0;
+	else if(stall == 1'b0) PC = PC+4;
+	out_nextpc = PC;
+end
+always @(negedge stall) begin
+	stallfinished = 1'b1;
 end
-
 endmodule

 module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
-
 input clk;
 input[4:0] readin1, readin2, writein;
 input[31:0] writedata;
@@ -11,7 +10,7 @@ reg[31:0] register[31:0];
 
 assign regout1 = register[readin1];
 assign regout2 = register[readin2];
-	
+
 initial begin
 	for(i=0; i<32; i=i+1) register[i] = 32'd0;
 end

 module ShiftLeft2(shiftinput, shiftoutput);
-
 input[31:0] shiftinput;
 output[31:0] shiftoutput;
 

 module SignExtend(signedinput, signedoutput);
-
 input[15:0] signedinput;
 output[31:0] signedoutput;
 

+module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 
+	in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 
+	out_stallsignal);
+input clk;
+input in_ex_regwrite, in_mem_regwrite, in_wb_regwrite;
+input[4:0] in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
+output reg out_stallsignal;
+
+initial out_stallsignal = 1'b0;
+
+always @(negedge clk) begin
+	if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_readreg_num1 || in_ex_writereg_num==in_readreg_num2)) begin
+		out_stallsignal = 1'b1;
+	end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_readreg_num1 || in_mem_writereg_num==in_readreg_num2)) begin
+		out_stallsignal = 1'b1;
+	end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_readreg_num1 || in_wb_writereg_num==in_readreg_num2)) begin
+		out_stallsignal = 1'b1;	
+	end else out_stallsignal = 1'b0;
+end
+
+endmodule
+
+

 module test;
+wire clk;
+wire stall;
+wire[4:0] in1, out1, out2, out3, out4, out5, out6;
+wire stall_1;
+
+assign stall_1 = 0;
+
+Clock clock(clk);
+testPC tpc(clk, stall, in1);
+testA ta1(clk, stall, in1, out1);
+testA ta2(clk, stall, out1, out2);
+testA ta3(clk, stall, out2, out3);
+testA ta4(clk, stall_1, out3, out4);
+testA ta5(clk, stall_1, out4, out5);
+testA ta6(clk, stall_1, out5, out6);
+testB stl(clk, out1, stall);
+
+initial begin
+end
+endmodule
+
+
+module testA(clk, stall, in1, out1);
+input clk, stall;
+input[4:0] in1;
+output reg[4:0] out1;
+
+reg[4:0] temp1;
+reg stallfinished;
+
+initial begin
+	temp1 = 5'b00000;
+	out1 = 5'b00000;
+	stallfinished = 1'b0;
+end
+
+always @(posedge clk) begin
+	if(stall == 1'b1) out1 <= 5'b00000;
+	else if(stallfinished == 1'b1) begin
+		out1 <= temp1;
+		stallfinished <= 1'b0;
+	end
+	else out1 <= in1;
+end
+always @(posedge stall) begin
+	temp1 = in1;
+end
+always @(negedge stall) begin
+	stallfinished = 1'b1;
+end
+endmodule
+
+
+module testB(clk, out1, stall);
+input clk;
+input[4:0] out1;
+output reg stall;
+
+integer i;
+
+initial begin
+	stall = 1'b0;
+	i = 0;
+end
+
+always @(negedge clk)
+	if(i > 0) i = i-1;
+	else begin
+		if(out1 == 5'b00101) begin
+			i = 2;
+			stall = 1'b1;
+		end
+		else stall = 1'b0;
+	end	
+endmodule
+
+
+module testPC(clk, stall, in1);
+input clk, stall;
+output reg[4:0] in1;
+
+reg[4:0] PC;
+
+initial begin
+	PC = 5'd0;
+end
+always @(posedge clk) begin
+	if(stall == 1'b0) PC <= PC+1;
+	in1 <= PC;
+end
+endmodule
+
+/*
+module test;
 
 wire clk;
 reg sig1;
@@ -22,22 +116,6 @@ initial begin
 	#100;
 end
 
-/*
-wire clk;
-reg[31:0] pc;
-wire[31:0] instr, tempPC;
-
-Clock clock(clk);
-InstructionFetch IF(clk, pc, instr, tempPC);
-
-initial begin
-	pc = 32'hfffffffc;
-end
-
-always @(negedge clk) begin
-	pc = pc + 4;
-end
-*/
 endmodule
 
 module testA(clk, sig1, in1, out1, out2);
@@ -52,3 +130,4 @@ always @(posedge clk) begin
 end
 
 endmodule
+*/
\ No newline at end of file

@@ -7,15 +7,15 @@ z2
 !i10e 25
 !i10f 100
 cModel Technology
-dD:/class/Capstone1/KNW_Project2/Project/Pipeline
+dC:/Modeltech_pe_edu_10.4a/examples
 vAdder
-!s110 1590758368
+Z0 !s110 1591621209
 !i10b 1
-!s100 C]ac0M5ljAN8jKk:YMWUe1
-IDi2UW;IAjgeEI=Re1d6>j0
-Z0 VDg1SIo80bB@j0V0VzS_@n1
-Z1 dD:/class/Capstone1/KNW_Project2/Project/MIPS
-Z2 w1590245372
+!s100 LKl?GBS:oo[A[hLP0Qb^_1
+IlbJEP?2C3Ya>zhzD12^S]1
+Z1 VDg1SIo80bB@j0V0VzS_@n1
+Z2 dD:/class/Capstone1/KNW_Project2/Project/MIPS
+w1591039528
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 L0 1
@@ -23,21 +23,21 @@ Z3 OP;L;10.4a;61
 r1
 !s85 0
 31
-!s108 1590758368.000000
+Z4 !s108 1591621208.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s101 -O0
 !i113 1
-Z4 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
+Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
 n@adder
 vALU
-Z5 !s110 1590758369
-!i10b 1
-!s100 8`_QAORX^JgbcU:FJndD:1
-I^ma26jUAmP4?NRZPY^4G=2
 R0
+!i10b 1
+!s100 z[hZ0^@Q34FnkzY3g0ioc2
+ImZ3]6XT73YVLGl?0_=9k33
 R1
-w1590755442
+R2
+w1591452276
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 L0 1
@@ -45,43 +45,43 @@ R3
 r1
 !s85 0
 31
-Z6 !s108 1590758369.000000
+Z6 !s108 1591621209.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@a@l@u
 vClock
-R5
+R0
 !i10b 1
 !s100 OWQXV6kDYiT>ChTOoCFa]2
-IQHn8SmB<S>;8X8GE^RU_a0
-R0
+IQ?l7WoBBid7ozVDn[8k:e3
 R1
 R2
-8D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
-FD:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+w1591110854
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
 L0 1
 R3
 r1
 !s85 0
 31
 R6
-!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@clock
 vControl
-R5
-!i10b 1
-!s100 RnD5[K2b[j8<X09[R7]kZ2
-I_4RCzG]R_IOaidB1NCK7D0
 R0
+!i10b 1
+!s100 4N9S2_;3jCoh7S5CM:UBB2
+IiJiDhRWdHkEd649hCz4P;1
 R1
-w1590757464
+R2
+w1591452194
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 L0 1
@@ -94,16 +94,16 @@ R6
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@control
 vDataMemory
-R5
-!i10b 1
-!s100 RT9n9HH7ShGYTRk0Zj<MK3
-IbciGN62QS2]SHi<BkL<2=2
 R0
+!i10b 1
+!s100 e=5E[GS05J<RCdT=KSMX_1
+I9=L>R4ccfGY8^T;U50LY?1
 R1
 R2
+w1591452257
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
 L0 1
@@ -116,82 +116,82 @@ R6
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@data@memory
 vEX_MEM
-R5
+Z7 !s110 1591621210
 !i10b 1
-!s100 ]8:X<?W@7Q@:C>XWDd6?W2
-ISC6^?55L`OXYAVlPjf`nE1
-R0
+!s100 7M;f[J6l]Q8I7]G9EaW4b2
+I4[]:7KKT=g2:;MLnikc863
 R1
-Z7 w1590758341
-Z8 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-Z9 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-L0 51
+R2
+Z8 w1591621089
+Z9 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+Z10 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+L0 142
 R3
 r1
 !s85 0
 31
-R6
-Z10 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
-Z11 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z11 !s108 1591621210.000000
+Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@e@x_@m@e@m
 vID_EX
-R5
+R7
 !i10b 1
-!s100 AOa7M@:@;]1<l5@<:]DoZ3
-I1^7Xh>glK<B3GFZz?nHKG1
-R0
+!s100 id94:21DzMBedgX<6MLIW3
+ILTL53m=Ci^KdWXiJ:6G`E2
 R1
-R7
+R2
 R8
 R9
-L0 14
+R10
+L0 45
 R3
 r1
 !s85 0
 31
-R6
-R10
 R11
+R12
+R13
 !s101 -O0
 !i113 1
-R4
+R5
 n@i@d_@e@x
 vIF_ID
-R5
+R7
 !i10b 1
-!s100 gnf82IK;Q2HN9lh8hggGU3
-I;=kYGK18[WJPiNhbdWnK>2
-R0
+!s100 ?M?9X@=b^flc3blH:Dn^g2
+I^7T81LjBP2[g8ie`ATZ=G2
 R1
-R7
+R2
 R8
 R9
+R10
 L0 1
 R3
 r1
 !s85 0
 31
-R6
-R10
 R11
+R12
+R13
 !s101 -O0
 !i113 1
-R4
+R5
 n@i@f_@i@d
 vInstructionMemory
-R5
+R7
 !i10b 1
-!s100 6FSBo3he?<YZH8SWT@?520
-I[UoXc[5<F^Vo]d2STIEaL3
-R0
+!s100 <VK`==0E@Llng:<adzYd80
+I6V??0<R5lO5JZ[eh2?Qo13
 R1
-w1590757768
+R2
+w1591579676
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 L0 1
@@ -199,43 +199,43 @@ R3
 r1
 !s85 0
 31
-R6
+R11
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@instruction@memory
 vMEM_WB
-R5
+R7
 !i10b 1
-!s100 U4fQaKDggSoeYLh<eCFgU0
-I@gj2Xh:PnQJOY356SH^a`2
-R0
+!s100 [HWKoHB:zC]dGeW[NDE]30
+IEjo6PSl[2V[fN=O@DA7W_0
 R1
-R7
+R2
 R8
 R9
-L0 81
+R10
+L0 173
 R3
 r1
 !s85 0
 31
-R6
-R10
 R11
+R12
+R13
 !s101 -O0
 !i113 1
-R4
+R5
 n@m@e@m_@w@b
 vMIPS_Pipeline
-R5
+R7
 !i10b 1
-!s100 d<3zzA7z4RnP`AU2`TaFC3
-Iao5jbloRQ>=BcXMPeBS3V0
-R0
+!s100 O:NALVmB^PBj5HkG<@2XA3
+I5L3]J:Nz<PQZe=N8z]::o3
 R1
-w1590757593
+R2
+w1591621120
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 L0 2
@@ -243,21 +243,21 @@ R3
 r1
 !s85 0
 31
-R6
+R11
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@m@i@p@s_@pipeline
 vMIPS_SingleCycle
-R5
+R7
 !i10b 1
-!s100 dPOY;3F4Z@[X550Mf8=`]2
-IQZkQc[MJbHhEVdg`K]7Hm0
-R0
+!s100 Zz<Q962j57a4IzW0mQ=5=1
+IMJcJ>deKe`cm>JGo56D8H2
 R1
-w1590757617
+R2
+w1591531598
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 L0 1
@@ -265,109 +265,109 @@ R3
 r1
 !s85 0
 31
-R6
+R11
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@m@i@p@s_@single@cycle
 vMux32bit
-R5
+R7
 !i10b 1
 !s100 foJG^YU75_eND1Og;6Z>O1
 II3=gjhQD0_cn8mlDL]@bi1
-R0
 R1
-Z12 w1590755668
-Z13 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
-Z14 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+R2
+Z14 w1591452448
+Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
 L0 15
 R3
 r1
 !s85 0
 31
-R6
-Z15 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
-Z16 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+R11
+Z17 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+Z18 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@mux32bit
 vMux5bit
-R5
+R7
 !i10b 1
 !s100 oSd=[kHDJb<:G7LN4]6@e3
 IfiVXg_aB2GQG7?F@=HcEi0
-R0
 R1
-R12
-R13
+R2
 R14
+R15
+R16
 L0 1
 R3
 r1
 !s85 0
 31
-R6
-R15
-R16
+R11
+R17
+R18
 !s101 -O0
 !i113 1
-R4
+R5
 n@mux5bit
 vMuxBranchSignal
-R5
+R7
 !i10b 1
 !s100 H1RKS9h`Y6QFX88CRc<g[0
 IGJT?gXMKEEWH?G^lPN79V2
-R0
 R1
-R12
-R13
+R2
 R14
+R15
+R16
 L0 29
 R3
 r1
 !s85 0
 31
-R6
-R15
-R16
+R11
+R17
+R18
 !s101 -O0
 !i113 1
-R4
+R5
 n@mux@branch@signal
 vPCcounter
-R5
+R7
 !i10b 1
-!s100 LU5jEj9S38k[SaIDeL1nG0
-I81MUZW]CnE2oaQhzNQ:^f3
-R0
+!s100 bjm68NMba>Y8oFGU?RHPK0
+IU;F]_bg19=g^Z:GGm6U:71
 R1
-R7
+R2
 R8
 R9
-L0 105
+R10
+L0 198
 R3
 r1
 !s85 0
 31
-R6
-R10
 R11
+R12
+R13
 !s101 -O0
 !i113 1
-R4
+R5
 n@p@ccounter
 vRegister
-R5
+Z19 !s110 1591621211
 !i10b 1
-!s100 Bdb0dL`fj[<g;4lO0DTA?2
-I]1XK2c]z?oKE2lz6^YJ@E2
-R0
+!s100 bC`<7GaPg=bDaZoUR<ADa0
+I<aR5RJ2c1Qba>GdC]KZCd2
 R1
 R2
+w1591452599
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
 L0 1
@@ -375,21 +375,21 @@ R3
 r1
 !s85 0
 31
-R6
+Z20 !s108 1591621211.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@register
 vShiftLeft2
-R5
+R19
 !i10b 1
-!s100 eI5Ec:gWMIfN>mTKQIBY93
-I>^Q9<62c;5[Hn[Q?e7H1W0
-R0
+!s100 ]Zje9D[f?jFRnJBn`OeHc1
+I]0TYJ]_7?FkOoY=2GlT5=3
 R1
 R2
+w1591039219
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
 L0 1
@@ -397,21 +397,21 @@ R3
 r1
 !s85 0
 31
-R6
+R20
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@shift@left2
 vSignExtend
-Z17 !s110 1590758370
+R19
 !i10b 1
-!s100 ahVKzC^1fD@70fO3WnVUV0
-Il`J_9Ud<V7MLm3fGkfTAf0
-R0
+!s100 =4eXcc0im3]S=Kk@o:eh32
+IFBiMm>fY8WE23A[Ye;CUj3
 R1
 R2
+w1591039196
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 L0 1
@@ -419,85 +419,107 @@ R3
 r1
 !s85 0
 31
-R6
+R20
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@sign@extend
 vStall
-R5
+R19
 !i10b 1
-!s100 DfdOH4n>:HLca08Dem_aV1
-IU:EDMN]H5b[DHo4cH[;FR3
-R0
+!s100 N?ZClBzVEP54JoYb>Ao9:3
+I:YbV=h@`DImW@Qc>>HXoc3
 R1
-w1590758365
-8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
-FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
-L0 2
+R2
+w1591618522
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
+L0 1
 R3
 r1
 !s85 0
 31
-R6
-!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+R20
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v|
 !s101 -O0
 !i113 1
-R4
+R5
 n@stall
 vtest
-R17
+Z21 !s110 1591621212
 !i10b 1
-!s100 k>03:b]McFVP5WBB2X74Q1
-I=8dVVickYZ@kW6ZABDlc_2
-R0
+!s100 KKL;hoG0Ojk_U;6H:]ViZ1
+Im`S61;3SN3Jlg_1AeFCP@3
 R1
-Z18 w1590335687
-Z19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
-Z20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+R2
+Z22 w1591501317
+Z23 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+Z24 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
 L0 1
 R3
 r1
 !s85 0
 31
-Z21 !s108 1590758370.000000
-Z22 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
-Z23 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
+R20
+Z25 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
+Z26 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
 !s101 -O0
 !i113 1
-R4
+R5
 vtestA
-R17
+R21
 !i10b 1
-!s100 N_c21cYjoS9<Wi;WjH:Qc0
-IdN8m[5hjJ3QH?beTSX`:T3
-R0
+!s100 Pkg?M_BZm@c5Y24EY;_H^3
+InVhi@1kAoF`f3N_KB]^7i3
 R1
-R18
-R19
-R20
-L0 43
+R2
+R22
+R23
+R24
+L0 24
 R3
 r1
 !s85 0
 31
+R20
+R25
+R26
+!s101 -O0
+!i113 1
+R5
+ntest@a
+vtestB
 R21
+!i10b 1
+!s100 S@=1_l7e?W`b88GB`bZQS0
+Il?;09cMF7Oe7LY1h4do2M3
+R1
+R2
 R22
 R23
+R24
+L0 55
+R3
+r1
+!s85 0
+31
+R20
+R25
+R26
 !s101 -O0
 !i113 1
-R4
-ntest@a
+R5
+ntest@b
 vtestbench
-R17
+!s110 1591621208
 !i10b 1
 !s100 OS>9h:91ecFHGVTRNVN]_2
 IR?_j2LXMem;jJUiXH@MhI0
-R0
 R1
+R2
 w1590428983
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
@@ -506,9 +528,31 @@ R3
 r1
 !s85 0
 31
-R21
+R4
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
 !s101 -O0
 !i113 1
-R4
+R5
+vtestPC
+R21
+!i10b 1
+!s100 L_L<o7@FSVAPYd[5blZAI1
+I8O06UXYD2fBn2meXg:jBC3
+R1
+R2
+R22
+R23
+R24
+L0 79
+R3
+r1
+!s85 0
+31
+R20
+R25
+R26
+!s101 -O0
+!i113 1
+R5
+ntest@p@c