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45064ffb 1 parent 41b10b57

오타 수정 및 stall 기능 추가(data hazard)

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Showing 23 changed files with 654 additions and 463 deletions
1 module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch); 1 module ALU(clk, aluin1, aluin2, aluctrl, aluout, alubranch);
2 -
3 input clk; 2 input clk;
4 input[31:0] aluin1, aluin2; 3 input[31:0] aluin1, aluin2;
5 input[3:0] aluctrl; 4 input[3:0] aluctrl;
6 output reg[31:0] aluout; 5 output reg[31:0] aluout;
7 -// output alubranch;
8 output reg[5:0] alubranch; 6 output reg[5:0] alubranch;
9 7
10 reg overflow; 8 reg overflow;
11 reg[63:0] temp; 9 reg[63:0] temp;
12 -reg[31:0] HI, LO; // HI, LO register for multiplication and division. 10 +reg[31:0] HI, LO; // HI, LO register for multiplication and division.
13 -reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division. 11 +reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division.
14 -
15 -// assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
16 12
17 initial begin 13 initial begin
18 temp = 64'h0000000000000000; 14 temp = 64'h0000000000000000;
...@@ -23,44 +19,45 @@ initial begin ...@@ -23,44 +19,45 @@ initial begin
23 end 19 end
24 20
25 always @(*) begin 21 always @(*) begin
26 -overflow = 0; 22 + overflow = 1'b0;
27 -case(aluctrl) 23 + alubranch = 6'b0;
28 - 4'b0000: aluout <= aluin1 & aluin2; // and 24 + case(aluctrl)
29 - 4'b0001: aluout <= aluin1 | aluin2; // or 25 + 4'b0000: aluout <= aluin1 & aluin2; // and
30 - 4'b0010: begin // add 26 + 4'b0001: aluout <= aluin1 | aluin2; // or
31 - aluout = aluin1 + aluin2; 27 + 4'b0010: begin // add
32 - overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection. 28 + aluout = aluin1 + aluin2;
33 - end 29 + overflow = aluin1[31]==aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
34 - 4'b0110: begin // sub 30 + end
35 - aluout = aluin1 - aluin2; 31 + 4'b0110: begin // sub
36 - overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection. 32 + aluout = aluin1 - aluin2;
37 - alubranch[0] = (aluout == 32'd0) ? 1'b1 : 1'b0; // beq 33 + overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
38 - alubranch[1] = (aluout != 32'd0) ? 1'b1 : 1'b0; // bne 34 + alubranch[0] = (aluout == 32'h00000000) ? 1'b1 : 1'b0; // beq
39 - alubranch[2] = (aluin1 > 32'd0) ? 1'b1 : 1'b0; // bgtz 35 + alubranch[1] = (aluout != 32'h00000000) ? 1'b1 : 1'b0; // bne
40 - alubranch[3] = (aluin1 < 32'd0) ? 1'b1 : 1'b0; // bltz 36 + alubranch[2] = (aluin1 > 32'h00000000) ? 1'b1 : 1'b0; // bgtz
41 - alubranch[4] = (aluin1 >= 32'd0) ? 1'b1 : 1'b0; // bgez 37 + alubranch[3] = (aluin1 < 32'h00000000) ? 1'b1 : 1'b0; // bltz
42 - alubranch[5] = (aluin1 <= 32'd0) ? 1'b1 : 1'b0; // blez 38 + alubranch[4] = (aluin1 >= 32'h00000000) ? 1'b1 : 1'b0; // bgez
43 - end 39 + alubranch[5] = (aluin1 <= 32'h00000000) ? 1'b1 : 1'b0; // blez
40 + end
44 41
45 - 4'b0111: begin // slt 42 + 4'b0111: begin // slt
46 - aluout[31:1] = {31{1'b0}}; 43 + aluout[31:1] = {31{1'b0}};
47 - aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0; 44 + aluout[0] = aluin1 < aluin2 ? 1'b1 : 1'b0;
48 - end 45 + end
49 - 4'b1000: begin // mult 46 + 4'b1000: begin // mult
50 - temp = aluin1 * aluin2; 47 + temp = aluin1 * aluin2;
51 - tempHI <= temp[63:32]; 48 + tempHI <= temp[63:32];
52 - tempLO <= temp[31:0]; 49 + tempLO <= temp[31:0];
53 - end 50 + end
54 - 4'b1001: begin // div 51 + 4'b1001: begin // div
55 - tempHI <= aluin1 % aluin2; 52 + tempHI <= aluin1 % aluin2;
56 - tempLO <= aluin1 / aluin2; 53 + tempLO <= aluin1 / aluin2;
57 - end 54 + end
58 - 4'b1010: aluout <= HI; // mfhi 55 + 4'b1010: aluout <= HI; // mfhi
59 - 4'b1011: aluout <= LO; // mflo 56 + 4'b1011: aluout <= LO; // mflo
60 - 4'b1100: aluout <= ~(aluin1 | aluin2); // nor 57 + 4'b1100: aluout <= ~(aluin1 | aluin2); // nor
61 - 4'b1101: aluout <= aluin1 ^ aluin2; // xor 58 + 4'b1101: aluout <= aluin1 ^ aluin2; // xor
62 - default: aluout <= 32'b0; 59 + default: aluout <= 32'h00000000;
63 -endcase 60 + endcase
64 end 61 end
65 62
66 always @(negedge clk) begin 63 always @(negedge clk) begin
......
1 module Adder(adderinput1, adderinput2, adderoutput); 1 module Adder(adderinput1, adderinput2, adderoutput);
2 -
3 input[31:0] adderinput1, adderinput2; 2 input[31:0] adderinput1, adderinput2;
4 output[31:0] adderoutput; 3 output[31:0] adderoutput;
5 4
......
1 module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg); 1 module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
2 -
3 input[5:0] opcode; 2 input[5:0] opcode;
4 input[4:0] rt; 3 input[4:0] rt;
5 input[5:0] funct; 4 input[5:0] funct;
......
1 module DataMemory(clk, address, writedata, memread, memwrite, readdata); 1 module DataMemory(clk, address, writedata, memread, memwrite, readdata);
2 -
3 input clk; 2 input clk;
4 input[31:0] address, writedata; 3 input[31:0] address, writedata;
5 input memread, memwrite; 4 input memread, memwrite;
6 -output[31:0] readdata; 5 +output reg[31:0] readdata;
7 6
7 +integer i;
8 reg[31:0] mem[255:0]; 8 reg[31:0] mem[255:0];
9 9
10 -assign readdata = memread ? mem[address/4] : 32'd0; 10 +initial begin
11 + for(i=0; i<256; i=i+1) mem[i] = 32'd0;
12 +end
11 13
12 always @(negedge clk) begin 14 always @(negedge clk) begin
15 + if(memread== 1'b1) begin
16 + readdata = mem[address/4];
17 + end
13 if(memwrite==1'b1) begin 18 if(memwrite==1'b1) begin
14 mem[address/4] = writedata; 19 mem[address/4] = writedata;
15 end 20 end
......
1 -/* Not Finished */
2 -module Stall(clk, in_readreg_num1, in_readreg_num2, in_writereg_num);
3 -
4 -input clk;
5 -input[4:0] in_readreg_num1, in_readreg_num2, in_writereg_num;
6 -
7 -reg[4:0] writeregs;
8 -
9 -endmodule
10 -
11 -
...@@ -7,24 +7,39 @@ reg[31:0] instr_mem[127:0]; ...@@ -7,24 +7,39 @@ reg[31:0] instr_mem[127:0];
7 7
8 initial begin 8 initial begin
9 instr_mem[0] = 32'd0; 9 instr_mem[0] = 32'd0;
10 -instr_mem[1] = 32'b00100100000010000000000011111111; // addi, $0 $8 255 10 +instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
11 -instr_mem[2] = 32'b00000001000010000100100000100000; // add, $8 $8 $9 11 +instr_mem[2] = 32'd0;
12 -instr_mem[3] = 32'b00000001000000000101000000100000; // add, $8 $0 $10 12 +instr_mem[3] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
13 -instr_mem[4] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1 13 +instr_mem[4] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
14 -instr_mem[5] = 32'd0; 14 +instr_mem[5] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
15 -instr_mem[6] = 32'b00000001000010010000000000011000; // mult, $8 $9 15 +instr_mem[6] = 32'b00100100000011010000000000000011; // addi, $0 $13 3
16 -instr_mem[7] = 32'd0; 16 +instr_mem[7] = 32'b00100100000010010000000000000001; // addi, $0 $9 1
17 -instr_mem[8] = 32'b00000000000000000110000000010000; // mfhi, $12 17 +instr_mem[8] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
18 -instr_mem[9] = 32'b00000000000000000110100000010010; // mflo, $13 18 +instr_mem[9] = 32'd0;
19 -instr_mem[10] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
20 -instr_mem[11] = 32'd0;
21 -instr_mem[12] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
22 -instr_mem[13] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
23 -instr_mem[14] = 32'd0;
24 -instr_mem[15] = 32'b00000000000000000000000000001000; // jr, $0
25 -
26 end 19 end
20 +/*
21 +initial begin
22 +out_clk = 1'b0;
27 23
24 +instr_mem[0] = 32'd0;
25 +instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
26 +instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
27 +instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9
28 +instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10
29 +instr_mem[5] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1
30 +instr_mem[6] = 32'd0;
31 +instr_mem[7] = 32'b00000001000010010000000000011000; // mult, $8 $9
32 +instr_mem[8] = 32'd0;
33 +instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12
34 +instr_mem[10] = 32'b00000000000000000110100000010010; // mflo, $13
35 +instr_mem[11] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
36 +instr_mem[12] = 32'd0;
37 +instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
38 +instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
39 +instr_mem[15] = 32'd0;
40 +instr_mem[16] = 32'b00000000000000000000000000001000; // jr, $0
41 +end
42 +*/
28 always @ (*) begin 43 always @ (*) begin
29 instruction = instr_mem[address/4]; 44 instruction = instr_mem[address/4];
30 end 45 end
......
1 -D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v 1 +D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module testbench 3 +-- Compiling module test
4 +-- Compiling module testA
5 +-- Compiling module testB
6 +-- Compiling module testPC
4 7
5 Top level modules: 8 Top level modules:
6 - testbench 9 + test
7 10
8 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v 11 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 12 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 --- Compiling module test 13 +-- Compiling module testbench
11 --- Compiling module testA
12 14
13 Top level modules: 15 Top level modules:
14 - test 16 + testbench
15 17
16 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 18 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
17 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 19 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -41,6 +43,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -41,6 +43,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
41 Top level modules: 43 Top level modules:
42 Register 44 Register
43 45
46 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
47 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
48 +-- Compiling module MIPS_Pipeline
49 +
50 +Top level modules:
51 + MIPS_Pipeline
52 +
44 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 53 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
45 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 54 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
46 -- Compiling module IF_ID 55 -- Compiling module IF_ID
...@@ -56,14 +65,7 @@ Top level modules: ...@@ -56,14 +65,7 @@ Top level modules:
56 MEM_WB 65 MEM_WB
57 PCcounter 66 PCcounter
58 67
59 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 68 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
60 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
61 --- Compiling module MIPS_Pipeline
62 -
63 -Top level modules:
64 - MIPS_Pipeline
65 -
66 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
67 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 69 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
68 -- Compiling module Stall 70 -- Compiling module Stall
69 71
...@@ -84,6 +86,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -84,6 +86,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
84 Top level modules: 86 Top level modules:
85 Control 87 Control
86 88
89 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
90 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
91 +-- Compiling module ALU
92 +
93 +Top level modules:
94 + ALU
95 +
87 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 96 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
88 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 97 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
89 -- Compiling module Mux5bit 98 -- Compiling module Mux5bit
...@@ -95,12 +104,12 @@ Top level modules: ...@@ -95,12 +104,12 @@ Top level modules:
95 Mux32bit 104 Mux32bit
96 MuxBranchSignal 105 MuxBranchSignal
97 106
98 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 107 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
99 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 108 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
100 --- Compiling module ALU 109 +-- Compiling module ShiftLeft2
101 110
102 Top level modules: 111 Top level modules:
103 - ALU 112 + ShiftLeft2
104 113
105 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} 114 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
106 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 115 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -109,14 +118,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -109,14 +118,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
109 Top level modules: 118 Top level modules:
110 DataMemory 119 DataMemory
111 120
112 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 121 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
113 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
114 --- Compiling module ShiftLeft2
115 -
116 -Top level modules:
117 - ShiftLeft2
118 -
119 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
120 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 122 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
121 -- Compiling module Clock 123 -- Compiling module Clock
122 124
......
...@@ -816,7 +816,7 @@ Resolution = ns ...@@ -816,7 +816,7 @@ Resolution = ns
816 UserTimeUnit = default 816 UserTimeUnit = default
817 817
818 ; Default run length 818 ; Default run length
819 -RunLength = 100 819 +RunLength = 100 ns
820 820
821 ; Maximum iterations that can be run without advancing simulation time 821 ; Maximum iterations that can be run without advancing simulation time
822 IterationLimit = 10000000 822 IterationLimit = 10000000
...@@ -2035,38 +2035,38 @@ Project_Version = 6 ...@@ -2035,38 +2035,38 @@ Project_Version = 6
2035 Project_DefaultLib = work 2035 Project_DefaultLib = work
2036 Project_SortMethod = unused 2036 Project_SortMethod = unused
2037 Project_Files_Count = 16 2037 Project_Files_Count = 16
2038 -Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v 2038 +Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
2039 -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590428983 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 2039 +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591501317 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
2040 -Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v 2040 +Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
2041 -Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590335687 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 2041 +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1590428983 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
2042 Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 2042 Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
2043 -Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 2043 +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039528 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
2044 Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 2044 Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
2045 -Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757617 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 2045 +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591531598 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
2046 Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 2046 Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
2047 -Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757768 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 2047 +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1591579676 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
2048 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 2048 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
2049 -Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 2049 +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452599 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
2050 Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 2050 Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
2051 -Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757593 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 2051 +Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1591621120 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
2052 Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 2052 Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
2053 -Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590758341 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0 2053 +Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591621089 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
2054 -Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 2054 +Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
2055 -Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1590758365 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 2055 +Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591618522 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
2056 Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 2056 Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
2057 -Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 2057 +Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039196 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
2058 Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 2058 Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
2059 -Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757464 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 2059 +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452194 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
2060 -Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 2060 +Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
2061 -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590755668 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 2061 +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452276 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
2062 -Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 2062 +Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
2063 -Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590755442 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 2063 +Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452448 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
2064 -Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v 2064 +Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
2065 -Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 2065 +Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039219 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
2066 -Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 2066 +Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
2067 -Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 2067 +Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452257 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
2068 -Project_File_15 = D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v 2068 +Project_File_15 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
2069 -Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 2069 +Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591110854 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
2070 Project_Sim_Count = 0 2070 Project_Sim_Count = 0
2071 Project_Folder_Count = 0 2071 Project_Folder_Count = 0
2072 Echo_Compile_Output = 0 2072 Echo_Compile_Output = 0
......
1 // Test Required 1 // Test Required
2 module MIPS_Pipeline; 2 module MIPS_Pipeline;
3 3
4 -wire clk; // clock 4 +wire clk;
5 +wire stallsignal;
5 wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC; 6 wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
6 7
7 wire[31:0] instr; // loaded instruction. 8 wire[31:0] instr; // loaded instruction.
...@@ -46,14 +47,21 @@ wire memwb_regwrite, memwb_memtoreg, memwb_jump; ...@@ -46,14 +47,21 @@ wire memwb_regwrite, memwb_memtoreg, memwb_jump;
46 wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump; 47 wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;
47 48
48 49
50 +
51 +wire tempstall;
52 +assign tempstall = 1'b0;
53 +
49 Clock clock(clk); 54 Clock clock(clk);
50 -PCcounter pccounter(clk, nextPC, instr_address); 55 +PCcounter pccounter(clk, stallsignal, nextPC, instr_address);
56 +Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite,
57 + ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,
58 + stallsignal);
51 59
52 // Instruction Fetch 60 // Instruction Fetch
53 InstructionMemory instrmem(instr_address, instr); 61 InstructionMemory instrmem(instr_address, instr);
54 -Adder add_pc4(PC, 32'h00000004, addPC4); 62 +Adder add_pc4(instr_address, 32'h00000004, addPC4);
55 63
56 -IF_ID ifid(clk, instr, addPC4, 64 +IF_ID ifid(clk, stallsignal, instr, addPC4,
57 ifid_instr, ifid_PC_4); 65 ifid_instr, ifid_PC_4);
58 66
59 // Instruction Decode 67 // Instruction Decode
...@@ -63,15 +71,15 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re ...@@ -63,15 +71,15 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re
63 SignExtend extend(ifid_instr[15:0], extend_output); 71 SignExtend extend(ifid_instr[15:0], extend_output);
64 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output); 72 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
65 73
66 -ID_EX idex(clk, reg_writereg1, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 74 +ID_EX idex(clk, stallsignal, reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg,
67 - reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, ifid_instr[25:21], ifid_instr[20:16], 75 + reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output,
68 - idex_writereg1, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 76 + idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg,
69 - idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump, idex_readreg_num1, idex_readreg_num2); 77 + idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
70 78
71 // Execute 79 // Execute
72 -Mux32bit mux_alusrc(idex_readdata2, idex_extend, idex_alusrc, alu_input2); 80 +Mux32bit mux_alusrc(idex_readdata2, idex_extenddata, idex_alusrc, alu_input2);
73 ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch); 81 ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch);
74 -ShiftLeft2 shiftBranch(idex_extend, shiftBranch_output); 82 +ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
75 Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch); 83 Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
76 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal); 84 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal);
77 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump); 85 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump);
...@@ -86,80 +94,16 @@ DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exm ...@@ -86,80 +94,16 @@ DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exm
86 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch); 94 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch);
87 95
88 MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 96 MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump,
89 - exmem_aluresult, mem_readdata, tempPC_branch, exmem_PCjump, 97 + exmem_aluresult, mem_readdata, exmem_PCjump, tempPC_branch,
90 memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 98 memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump,
91 - memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump); 99 + memwb_aluresult, memwb_memreaddata, memwb_PCjump, memwb_PCbranch);
92 100
93 // Writeback 101 // Writeback
94 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, reg_writedata); 102 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, reg_writedata);
95 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC); 103 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC);
96 104
97 105
98 -
99 -
100 -always @(posedge clk) begin
101 -
102 -end
103 -
104 -/*
105 -wire clk; // clock
106 -reg[31:0] PC, instr_address;
107 -
108 -// IF - ID
109 -wire[31:0] if_id_instruction, if_id_pc_4;
110 -
111 -// ID - EX
112 -wire[31:0] id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump;
113 -wire[4:0] id_ex_writereg, id_hh_readreg1, id_hh_readreg2;
114 -wire id_ex_regwrite, id_ex_alusrc, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg;
115 -wire[3:0] id_ex_aluctrl;
116 -
117 -// EX - MEM
118 -wire[31:0] ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch;
119 -wire[4:0] ex_mem_writereg;
120 -wire ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump;
121 -
122 -// MEM - WB
123 -wire[4:0] mem_wb_writereg_num;
124 -wire mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump;
125 -wire[31:0] mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump;
126 -
127 -// WB - etc.
128 -wire wb_id_regwrite;
129 -wire[4:0] wb_id_writereg;
130 -wire[31:0] wb_id_reg_writedata;
131 -wire[31:0] wb_nextPC;
132 -
133 -Clock clock(clk);
134 -
135 -InstructionFetch IF(clk, PC, if_id_instruction, if_id_pc_4);
136 -
137 -InstructionDecode ID(clk, if_id_instruction, if_id_pc_4, wb_id_writereg, wb_id_reg_writedata, wb_id_regwrite,
138 - id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
139 - id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump);
140 -
141 -Execute EX(clk, id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
142 - id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump,
143 - ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump,
144 - ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch);
145 -
146 -Mem MEM(clk, ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump,
147 - ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch,
148 - mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump);
149 -
150 -WriteBack WB(clk, mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump,
151 - wb_id_regwrite, wb_id_writereg, wb_id_reg_writedata, wb_nextPC);
152 -
153 -initial begin
154 - PC = 32'hfffffffc;
155 -end
156 -
157 always @(posedge clk) begin 106 always @(posedge clk) begin
158 - instr_address = PC;
159 end 107 end
160 108
161 -always @(negedge clk) begin
162 - PC = PC + 4;
163 -end
164 -*/
165 endmodule 109 endmodule
......
1 module MIPS_SingleCycle; 1 module MIPS_SingleCycle;
2 2
3 -wire clk; // clock 3 +wire clk; // clock
4 -reg[31:0] PC; // program counter 4 +reg[31:0] PC; // program counter
5 reg[31:0] instr_address; 5 reg[31:0] instr_address;
6 wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC; 6 wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
7 7
8 -wire[31:0] instr; // loaded instruction. 8 +wire[31:0] instr; // loaded instruction.
9 9
10 -wire[4:0] reg_writereg1; // register number for the write data. 10 +wire[4:0] reg_writereg1; // register number for the write data.
11 -wire[31:0] reg_writedata; // data that will be written in the register. 11 +wire[31:0] reg_writedata; // data that will be written in the register.
12 -wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. 12 +wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
13 13
14 -wire[31:0] alu_input2; // input data of ALU. 14 +wire[31:0] alu_input2; // input data of ALU.
15 -wire[31:0] alu_result; // result data of ALU. 15 +wire[31:0] alu_result; // result data of ALU.
16 -wire[5:0] alu_branch; // indicator for branch operation. 16 +wire[5:0] alu_branch; // indicator for branch operation.
17 17
18 -wire[31:0] mem_readdata; // data from the requested address. 18 +wire[31:0] mem_readdata; // data from the requested address.
19 19
20 wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal; 20 wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
21 wire[3:0] ctrl_aluctrl; 21 wire[3:0] ctrl_aluctrl;
22 -wire[2:0] ctrl_branch; // control signals. 22 +wire[2:0] ctrl_branch; // control signals.
23 23
24 wire[31:0] extend_output; 24 wire[31:0] extend_output;
25 25
26 wire[31:0] shiftBranch_output; 26 wire[31:0] shiftBranch_output;
27 wire[31:0] shiftJump_output; 27 wire[31:0] shiftJump_output;
28 28
29 +
29 Clock clock(clk); 30 Clock clock(clk);
30 InstructionMemory instrmem(instr_address, instr); 31 InstructionMemory instrmem(instr_address, instr);
31 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2); 32 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
32 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch); 33 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
33 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata); 34 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
34 Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg); 35 Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
36 +
35 Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1); 37 Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
36 MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal); 38 MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal);
37 Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2); 39 Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
......
...@@ -44,3 +44,4 @@ always @(*) begin ...@@ -44,3 +44,4 @@ always @(*) begin
44 end 44 end
45 45
46 endmodule 46 endmodule
47 +
......
1 -module IF_ID(clk, in_instruction, in_PC_4, 1 +module IF_ID(clk, stall, in_instruction, in_PC_4,
2 out_instruction, out_PC_4); 2 out_instruction, out_PC_4);
3 -input clk; 3 +input clk, stall;
4 +
4 input[31:0] in_instruction, in_PC_4; 5 input[31:0] in_instruction, in_PC_4;
6 +
5 output reg[31:0] out_instruction, out_PC_4; 7 output reg[31:0] out_instruction, out_PC_4;
6 8
9 +reg[31:0] temp_instruction, temp_PC_4;
10 +
11 +reg stallfinished;
12 +
13 +initial begin
14 + stallfinished = 1'b0;
15 +end
16 +
7 always @(posedge clk) begin 17 always @(posedge clk) begin
8 - out_instruction <= in_instruction; 18 +
9 - out_PC_4 <= in_PC_4; 19 + if(stall == 1'b1) begin
20 + out_instruction <= 32'h00000000;
21 + out_PC_4 <= 32'h00000000;
22 + end
23 + else if(stallfinished == 1'b1) begin
24 + out_instruction <= temp_instruction;
25 + out_PC_4 <= temp_PC_4;
26 +
27 + stallfinished = 1'b0;
28 + end
29 + else begin
30 + out_instruction <= in_instruction;
31 + out_PC_4 <= in_PC_4;
32 + end
33 +end
34 +
35 +always @(posedge stall) begin
36 + temp_instruction <= out_instruction;
37 + temp_PC_4 <= out_PC_4;
38 +end
39 +always @(negedge stall) begin
40 + stallfinished = 1'b1;
10 end 41 end
11 endmodule 42 endmodule
12 43
13 44
14 -module ID_EX(clk, in_writereg_num, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 45 +module ID_EX(clk, stall, in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg,
15 - in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2, 46 + in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump,
16 - out_writereg_num, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 47 + out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg,
17 - out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2); 48 + out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
18 -input clk; 49 +input clk, stall;
19 -input[4:0] in_writereg_num; 50 +
20 -input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg; 51 +input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
52 +input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg;
21 input[3:0] in_aluctrl; 53 input[3:0] in_aluctrl;
22 -input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2; 54 +input[2:0] in_branch;
23 -output reg[4:0] out_writereg_num; 55 +input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump;
24 -output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg; 56 +
57 +output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2;
58 +output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg;
25 output reg[3:0] out_aluctrl; 59 output reg[3:0] out_aluctrl;
26 -output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2; 60 +output reg[2:0] out_branch;
61 +output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
62 +
63 +reg stallfinished;
27 64
65 +initial begin
66 + stallfinished = 1'b0;
67 +end
28 always @(posedge clk) begin 68 always @(posedge clk) begin
29 - out_writereg_num <= in_writereg_num; 69 + if(stall == 1'b1) begin
30 - out_regwrite <= in_regwrite; 70 + out_writereg_num <= 5'b00000;
31 - out_alusrc <= in_alusrc; 71 + out_readreg_num1 <= 5'b00000;
32 - out_aluctrl <= in_aluctrl; 72 + out_readreg_num2 <= 5'b00000;
33 - out_memread <= in_memread; 73 +
34 - out_memwrite <= in_memwrite; 74 + out_regwrite <= 1'b0;
35 - out_memtoreg <= in_memtoreg; 75 + out_alusrc <= 1'b0;
36 - out_branch <= in_branch; 76 + out_aluctrl <= 4'b0000;
37 - out_jump <= in_jump; 77 + out_memread <= 1'b0;
38 - out_jumpreg <= in_jumpreg; 78 + out_memwrite <= 1'b0;
39 - 79 + out_memtoreg <= 1'b0;
40 - out_readdata1 <= in_readdata1; 80 + out_branch <= 3'b000;
41 - out_readdata2 <= in_readdata2; 81 + out_jump <= 1'b0;
42 - out_extenddata <= in_extenddata; 82 + out_jumpreg <= 1'b0;
43 - out_PC_4 <= out_PC_4; 83 +
44 - out_tempPCjump <= in_tempPCjump; 84 + out_readdata1 <= 32'h00000000;
45 - out_readreg_num1 <= in_readreg_num1; 85 + out_readdata2 <= 32'h00000000;
46 - out_readreg_num2 <= in_readreg_num2; 86 + out_extenddata <= 32'h00000000;
87 + out_PC_4 <= 32'h00000000;
88 + out_tempPCjump <= 32'h00000000;
89 + end
90 + else if(stallfinished == 1'b1) begin
91 + out_writereg_num <= 5'b00000;
92 + out_readreg_num1 <= 5'b00000;
93 + out_readreg_num2 <= 5'b00000;
94 +
95 + out_regwrite <= 1'b0;
96 + out_alusrc <= 1'b0;
97 + out_aluctrl <= 4'b0000;
98 + out_memread <= 1'b0;
99 + out_memwrite <= 1'b0;
100 + out_memtoreg <= 1'b0;
101 + out_branch <= 3'b000;
102 + out_jump <= 1'b0;
103 + out_jumpreg <= 1'b0;
104 +
105 + out_readdata1 <= 32'h00000000;
106 + out_readdata2 <= 32'h00000000;
107 + out_extenddata <= 32'h00000000;
108 + out_PC_4 <= 32'h00000000;
109 + out_tempPCjump <= 32'h00000000;
110 +
111 + stallfinished = 1'b0;
112 + end
113 + else begin
114 + out_writereg_num <= in_writereg_num;
115 + out_readreg_num1 <= in_readreg_num1;
116 + out_readreg_num2 <= in_readreg_num2;
117 +
118 + out_regwrite <= in_regwrite;
119 + out_alusrc <= in_alusrc;
120 + out_aluctrl <= in_aluctrl;
121 + out_memread <= in_memread;
122 + out_memwrite <= in_memwrite;
123 + out_memtoreg <= in_memtoreg;
124 + out_branch <= in_branch;
125 + out_jump <= in_jump;
126 + out_jumpreg <= in_jumpreg;
127 +
128 + out_readdata1 <= in_readdata1;
129 + out_readdata2 <= in_readdata2;
130 + out_extenddata <= in_extenddata;
131 + out_PC_4 <= in_PC_4;
132 + out_tempPCjump <= in_tempPCjump;
133 + end
134 +end
135 +always @(negedge stall) begin
136 + stallfinished = 1'b1;
47 end 137 end
138 +
48 endmodule 139 endmodule
49 140
50 141
...@@ -53,6 +144,7 @@ module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_mem ...@@ -53,6 +144,7 @@ module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_mem
53 out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 144 out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump,
54 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch); 145 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
55 input clk; 146 input clk;
147 +
56 input[4:0] in_writereg_num; 148 input[4:0] in_writereg_num;
57 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump; 149 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
58 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch; 150 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
...@@ -79,8 +171,9 @@ endmodule ...@@ -79,8 +171,9 @@ endmodule
79 171
80 172
81 module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 173 module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump,
82 - out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCbranch, out_PCjump); 174 + out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCjump, out_PCbranch);
83 input clk; 175 input clk;
176 +
84 input[4:0] in_writereg_num; 177 input[4:0] in_writereg_num;
85 input in_regwrite, in_memtoreg, in_jump; 178 input in_regwrite, in_memtoreg, in_jump;
86 input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump; 179 input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
...@@ -96,31 +189,33 @@ always @(posedge clk) begin ...@@ -96,31 +189,33 @@ always @(posedge clk) begin
96 189
97 out_aluresult <= in_aluresult; 190 out_aluresult <= in_aluresult;
98 out_memreaddata <= in_memreaddata; 191 out_memreaddata <= in_memreaddata;
99 - out_PCbranch <= out_PCbranch; 192 + out_PCjump <= in_PCjump;
100 - out_PCjump <= out_PCjump; 193 + out_PCbranch <= in_PCbranch;
101 end 194 end
102 endmodule 195 endmodule
103 196
104 /* Not Finished */ 197 /* Not Finished */
105 -module PCcounter(clk, in_pc, out_nextpc); 198 +module PCcounter(clk, stall, in_pc, out_nextpc);
106 -input clk; 199 +input clk, stall;
200 +
107 input[31:0] in_pc; 201 input[31:0] in_pc;
108 output reg[31:0] out_nextpc; 202 output reg[31:0] out_nextpc;
203 +
109 reg[31:0] PC; 204 reg[31:0] PC;
205 +reg stallfinished;
110 206
111 initial begin 207 initial begin
112 PC = 32'h00000000; 208 PC = 32'h00000000;
209 + stallfinished = 1'b1;
113 end 210 end
114 211
115 always @(posedge clk) begin 212 always @(posedge clk) begin
116 -/* 213 +
117 - case(in_pc[31]) // if in_pc is available, PC = in_pc. 214 + if(stallfinished == 1'b1) stallfinished = 1'b0;
118 - 1'b0: PC = in_pc; 215 + else if(stall == 1'b0) PC = PC+4;
119 - 1'b1: PC = in_pc; 216 + out_nextpc = PC;
120 - endcase 217 +end
121 -*/ 218 +always @(negedge stall) begin
122 - PC <= PC+4; 219 + stallfinished = 1'b1;
123 - out_nextpc <= PC;
124 end 220 end
125 -
126 endmodule 221 endmodule
......
1 module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2); 1 module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
2 -
3 input clk; 2 input clk;
4 input[4:0] readin1, readin2, writein; 3 input[4:0] readin1, readin2, writein;
5 input[31:0] writedata; 4 input[31:0] writedata;
...@@ -11,7 +10,7 @@ reg[31:0] register[31:0]; ...@@ -11,7 +10,7 @@ reg[31:0] register[31:0];
11 10
12 assign regout1 = register[readin1]; 11 assign regout1 = register[readin1];
13 assign regout2 = register[readin2]; 12 assign regout2 = register[readin2];
14 - 13 +
15 initial begin 14 initial begin
16 for(i=0; i<32; i=i+1) register[i] = 32'd0; 15 for(i=0; i<32; i=i+1) register[i] = 32'd0;
17 end 16 end
......
1 module ShiftLeft2(shiftinput, shiftoutput); 1 module ShiftLeft2(shiftinput, shiftoutput);
2 -
3 input[31:0] shiftinput; 2 input[31:0] shiftinput;
4 output[31:0] shiftoutput; 3 output[31:0] shiftoutput;
5 4
......
1 module SignExtend(signedinput, signedoutput); 1 module SignExtend(signedinput, signedoutput);
2 -
3 input[15:0] signedinput; 2 input[15:0] signedinput;
4 output[31:0] signedoutput; 3 output[31:0] signedoutput;
5 4
......
1 +module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite,
2 + in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
3 + out_stallsignal);
4 +input clk;
5 +input in_ex_regwrite, in_mem_regwrite, in_wb_regwrite;
6 +input[4:0] in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
7 +output reg out_stallsignal;
8 +
9 +initial out_stallsignal = 1'b0;
10 +
11 +always @(negedge clk) begin
12 + if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_readreg_num1 || in_ex_writereg_num==in_readreg_num2)) begin
13 + out_stallsignal = 1'b1;
14 + end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_readreg_num1 || in_mem_writereg_num==in_readreg_num2)) begin
15 + out_stallsignal = 1'b1;
16 + end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_readreg_num1 || in_wb_writereg_num==in_readreg_num2)) begin
17 + out_stallsignal = 1'b1;
18 + end else out_stallsignal = 1'b0;
19 +end
20 +
21 +endmodule
22 +
23 +
1 module test; 1 module test;
2 +wire clk;
3 +wire stall;
4 +wire[4:0] in1, out1, out2, out3, out4, out5, out6;
5 +wire stall_1;
6 +
7 +assign stall_1 = 0;
8 +
9 +Clock clock(clk);
10 +testPC tpc(clk, stall, in1);
11 +testA ta1(clk, stall, in1, out1);
12 +testA ta2(clk, stall, out1, out2);
13 +testA ta3(clk, stall, out2, out3);
14 +testA ta4(clk, stall_1, out3, out4);
15 +testA ta5(clk, stall_1, out4, out5);
16 +testA ta6(clk, stall_1, out5, out6);
17 +testB stl(clk, out1, stall);
18 +
19 +initial begin
20 +end
21 +endmodule
22 +
23 +
24 +module testA(clk, stall, in1, out1);
25 +input clk, stall;
26 +input[4:0] in1;
27 +output reg[4:0] out1;
28 +
29 +reg[4:0] temp1;
30 +reg stallfinished;
31 +
32 +initial begin
33 + temp1 = 5'b00000;
34 + out1 = 5'b00000;
35 + stallfinished = 1'b0;
36 +end
37 +
38 +always @(posedge clk) begin
39 + if(stall == 1'b1) out1 <= 5'b00000;
40 + else if(stallfinished == 1'b1) begin
41 + out1 <= temp1;
42 + stallfinished <= 1'b0;
43 + end
44 + else out1 <= in1;
45 +end
46 +always @(posedge stall) begin
47 + temp1 = in1;
48 +end
49 +always @(negedge stall) begin
50 + stallfinished = 1'b1;
51 +end
52 +endmodule
53 +
54 +
55 +module testB(clk, out1, stall);
56 +input clk;
57 +input[4:0] out1;
58 +output reg stall;
59 +
60 +integer i;
61 +
62 +initial begin
63 + stall = 1'b0;
64 + i = 0;
65 +end
66 +
67 +always @(negedge clk)
68 + if(i > 0) i = i-1;
69 + else begin
70 + if(out1 == 5'b00101) begin
71 + i = 2;
72 + stall = 1'b1;
73 + end
74 + else stall = 1'b0;
75 + end
76 +endmodule
77 +
78 +
79 +module testPC(clk, stall, in1);
80 +input clk, stall;
81 +output reg[4:0] in1;
82 +
83 +reg[4:0] PC;
84 +
85 +initial begin
86 + PC = 5'd0;
87 +end
88 +always @(posedge clk) begin
89 + if(stall == 1'b0) PC <= PC+1;
90 + in1 <= PC;
91 +end
92 +endmodule
93 +
94 +/*
95 +module test;
2 96
3 wire clk; 97 wire clk;
4 reg sig1; 98 reg sig1;
...@@ -22,22 +116,6 @@ initial begin ...@@ -22,22 +116,6 @@ initial begin
22 #100; 116 #100;
23 end 117 end
24 118
25 -/*
26 -wire clk;
27 -reg[31:0] pc;
28 -wire[31:0] instr, tempPC;
29 -
30 -Clock clock(clk);
31 -InstructionFetch IF(clk, pc, instr, tempPC);
32 -
33 -initial begin
34 - pc = 32'hfffffffc;
35 -end
36 -
37 -always @(negedge clk) begin
38 - pc = pc + 4;
39 -end
40 -*/
41 endmodule 119 endmodule
42 120
43 module testA(clk, sig1, in1, out1, out2); 121 module testA(clk, sig1, in1, out1, out2);
...@@ -52,3 +130,4 @@ always @(posedge clk) begin ...@@ -52,3 +130,4 @@ always @(posedge clk) begin
52 end 130 end
53 131
54 endmodule 132 endmodule
133 +*/
...\ No newline at end of file ...\ No newline at end of file
......
...@@ -7,15 +7,15 @@ z2 ...@@ -7,15 +7,15 @@ z2
7 !i10e 25 7 !i10e 25
8 !i10f 100 8 !i10f 100
9 cModel Technology 9 cModel Technology
10 -dD:/class/Capstone1/KNW_Project2/Project/Pipeline 10 +dC:/Modeltech_pe_edu_10.4a/examples
11 vAdder 11 vAdder
12 -!s110 1590758368 12 +Z0 !s110 1591621209
13 !i10b 1 13 !i10b 1
14 -!s100 C]ac0M5ljAN8jKk:YMWUe1 14 +!s100 LKl?GBS:oo[A[hLP0Qb^_1
15 -IDi2UW;IAjgeEI=Re1d6>j0 15 +IlbJEP?2C3Ya>zhzD12^S]1
16 -Z0 VDg1SIo80bB@j0V0VzS_@n1 16 +Z1 VDg1SIo80bB@j0V0VzS_@n1
17 -Z1 dD:/class/Capstone1/KNW_Project2/Project/MIPS 17 +Z2 dD:/class/Capstone1/KNW_Project2/Project/MIPS
18 -Z2 w1590245372 18 +w1591039528
19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
21 L0 1 21 L0 1
...@@ -23,21 +23,21 @@ Z3 OP;L;10.4a;61 ...@@ -23,21 +23,21 @@ Z3 OP;L;10.4a;61
23 r1 23 r1
24 !s85 0 24 !s85 0
25 31 25 31
26 -!s108 1590758368.000000 26 +Z4 !s108 1591621208.000000
27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
29 !s101 -O0 29 !s101 -O0
30 !i113 1 30 !i113 1
31 -Z4 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0 31 +Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
32 n@adder 32 n@adder
33 vALU 33 vALU
34 -Z5 !s110 1590758369
35 -!i10b 1
36 -!s100 8`_QAORX^JgbcU:FJndD:1
37 -I^ma26jUAmP4?NRZPY^4G=2
38 R0 34 R0
35 +!i10b 1
36 +!s100 z[hZ0^@Q34FnkzY3g0ioc2
37 +ImZ3]6XT73YVLGl?0_=9k33
39 R1 38 R1
40 -w1590755442 39 +R2
40 +w1591452276
41 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 41 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
42 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 42 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
43 L0 1 43 L0 1
...@@ -45,43 +45,43 @@ R3 ...@@ -45,43 +45,43 @@ R3
45 r1 45 r1
46 !s85 0 46 !s85 0
47 31 47 31
48 -Z6 !s108 1590758369.000000 48 +Z6 !s108 1591621209.000000
49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
51 !s101 -O0 51 !s101 -O0
52 !i113 1 52 !i113 1
53 -R4 53 +R5
54 n@a@l@u 54 n@a@l@u
55 vClock 55 vClock
56 -R5 56 +R0
57 !i10b 1 57 !i10b 1
58 !s100 OWQXV6kDYiT>ChTOoCFa]2 58 !s100 OWQXV6kDYiT>ChTOoCFa]2
59 -IQHn8SmB<S>;8X8GE^RU_a0 59 +IQ?l7WoBBid7ozVDn[8k:e3
60 -R0
61 R1 60 R1
62 R2 61 R2
63 -8D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v 62 +w1591110854
64 -FD:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v 63 +8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
64 +FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
65 L0 1 65 L0 1
66 R3 66 R3
67 r1 67 r1
68 !s85 0 68 !s85 0
69 31 69 31
70 R6 70 R6
71 -!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v| 71 +!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
72 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v| 72 +!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
73 !s101 -O0 73 !s101 -O0
74 !i113 1 74 !i113 1
75 -R4 75 +R5
76 n@clock 76 n@clock
77 vControl 77 vControl
78 -R5
79 -!i10b 1
80 -!s100 RnD5[K2b[j8<X09[R7]kZ2
81 -I_4RCzG]R_IOaidB1NCK7D0
82 R0 78 R0
79 +!i10b 1
80 +!s100 4N9S2_;3jCoh7S5CM:UBB2
81 +IiJiDhRWdHkEd649hCz4P;1
83 R1 82 R1
84 -w1590757464 83 +R2
84 +w1591452194
85 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 85 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
86 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 86 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
87 L0 1 87 L0 1
...@@ -94,16 +94,16 @@ R6 ...@@ -94,16 +94,16 @@ R6
94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
95 !s101 -O0 95 !s101 -O0
96 !i113 1 96 !i113 1
97 -R4 97 +R5
98 n@control 98 n@control
99 vDataMemory 99 vDataMemory
100 -R5
101 -!i10b 1
102 -!s100 RT9n9HH7ShGYTRk0Zj<MK3
103 -IbciGN62QS2]SHi<BkL<2=2
104 R0 100 R0
101 +!i10b 1
102 +!s100 e=5E[GS05J<RCdT=KSMX_1
103 +I9=L>R4ccfGY8^T;U50LY?1
105 R1 104 R1
106 R2 105 R2
106 +w1591452257
107 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v 107 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
108 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v 108 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
109 L0 1 109 L0 1
...@@ -116,82 +116,82 @@ R6 ...@@ -116,82 +116,82 @@ R6
116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
117 !s101 -O0 117 !s101 -O0
118 !i113 1 118 !i113 1
119 -R4 119 +R5
120 n@data@memory 120 n@data@memory
121 vEX_MEM 121 vEX_MEM
122 -R5 122 +Z7 !s110 1591621210
123 !i10b 1 123 !i10b 1
124 -!s100 ]8:X<?W@7Q@:C>XWDd6?W2 124 +!s100 7M;f[J6l]Q8I7]G9EaW4b2
125 -ISC6^?55L`OXYAVlPjf`nE1 125 +I4[]:7KKT=g2:;MLnikc863
126 -R0
127 R1 126 R1
128 -Z7 w1590758341 127 +R2
129 -Z8 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 128 +Z8 w1591621089
130 -Z9 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 129 +Z9 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
131 -L0 51 130 +Z10 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
131 +L0 142
132 R3 132 R3
133 r1 133 r1
134 !s85 0 134 !s85 0
135 31 135 31
136 -R6 136 +Z11 !s108 1591621210.000000
137 -Z10 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 137 +Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
138 -Z11 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 138 +Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
139 !s101 -O0 139 !s101 -O0
140 !i113 1 140 !i113 1
141 -R4 141 +R5
142 n@e@x_@m@e@m 142 n@e@x_@m@e@m
143 vID_EX 143 vID_EX
144 -R5 144 +R7
145 !i10b 1 145 !i10b 1
146 -!s100 AOa7M@:@;]1<l5@<:]DoZ3 146 +!s100 id94:21DzMBedgX<6MLIW3
147 -I1^7Xh>glK<B3GFZz?nHKG1 147 +ILTL53m=Ci^KdWXiJ:6G`E2
148 -R0
149 R1 148 R1
150 -R7 149 +R2
151 R8 150 R8
152 R9 151 R9
153 -L0 14 152 +R10
153 +L0 45
154 R3 154 R3
155 r1 155 r1
156 !s85 0 156 !s85 0
157 31 157 31
158 -R6
159 -R10
160 R11 158 R11
159 +R12
160 +R13
161 !s101 -O0 161 !s101 -O0
162 !i113 1 162 !i113 1
163 -R4 163 +R5
164 n@i@d_@e@x 164 n@i@d_@e@x
165 vIF_ID 165 vIF_ID
166 -R5 166 +R7
167 !i10b 1 167 !i10b 1
168 -!s100 gnf82IK;Q2HN9lh8hggGU3 168 +!s100 ?M?9X@=b^flc3blH:Dn^g2
169 -I;=kYGK18[WJPiNhbdWnK>2 169 +I^7T81LjBP2[g8ie`ATZ=G2
170 -R0
171 R1 170 R1
172 -R7 171 +R2
173 R8 172 R8
174 R9 173 R9
174 +R10
175 L0 1 175 L0 1
176 R3 176 R3
177 r1 177 r1
178 !s85 0 178 !s85 0
179 31 179 31
180 -R6
181 -R10
182 R11 180 R11
181 +R12
182 +R13
183 !s101 -O0 183 !s101 -O0
184 !i113 1 184 !i113 1
185 -R4 185 +R5
186 n@i@f_@i@d 186 n@i@f_@i@d
187 vInstructionMemory 187 vInstructionMemory
188 -R5 188 +R7
189 !i10b 1 189 !i10b 1
190 -!s100 6FSBo3he?<YZH8SWT@?520 190 +!s100 <VK`==0E@Llng:<adzYd80
191 -I[UoXc[5<F^Vo]d2STIEaL3 191 +I6V??0<R5lO5JZ[eh2?Qo13
192 -R0
193 R1 192 R1
194 -w1590757768 193 +R2
194 +w1591579676
195 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 195 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
196 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 196 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
197 L0 1 197 L0 1
...@@ -199,43 +199,43 @@ R3 ...@@ -199,43 +199,43 @@ R3
199 r1 199 r1
200 !s85 0 200 !s85 0
201 31 201 31
202 -R6 202 +R11
203 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 203 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
204 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 204 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
205 !s101 -O0 205 !s101 -O0
206 !i113 1 206 !i113 1
207 -R4 207 +R5
208 n@instruction@memory 208 n@instruction@memory
209 vMEM_WB 209 vMEM_WB
210 -R5 210 +R7
211 !i10b 1 211 !i10b 1
212 -!s100 U4fQaKDggSoeYLh<eCFgU0 212 +!s100 [HWKoHB:zC]dGeW[NDE]30
213 -I@gj2Xh:PnQJOY356SH^a`2 213 +IEjo6PSl[2V[fN=O@DA7W_0
214 -R0
215 R1 214 R1
216 -R7 215 +R2
217 R8 216 R8
218 R9 217 R9
219 -L0 81 218 +R10
219 +L0 173
220 R3 220 R3
221 r1 221 r1
222 !s85 0 222 !s85 0
223 31 223 31
224 -R6
225 -R10
226 R11 224 R11
225 +R12
226 +R13
227 !s101 -O0 227 !s101 -O0
228 !i113 1 228 !i113 1
229 -R4 229 +R5
230 n@m@e@m_@w@b 230 n@m@e@m_@w@b
231 vMIPS_Pipeline 231 vMIPS_Pipeline
232 -R5 232 +R7
233 !i10b 1 233 !i10b 1
234 -!s100 d<3zzA7z4RnP`AU2`TaFC3 234 +!s100 O:NALVmB^PBj5HkG<@2XA3
235 -Iao5jbloRQ>=BcXMPeBS3V0 235 +I5L3]J:Nz<PQZe=N8z]::o3
236 -R0
237 R1 236 R1
238 -w1590757593 237 +R2
238 +w1591621120
239 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 239 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
240 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 240 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
241 L0 2 241 L0 2
...@@ -243,21 +243,21 @@ R3 ...@@ -243,21 +243,21 @@ R3
243 r1 243 r1
244 !s85 0 244 !s85 0
245 31 245 31
246 -R6 246 +R11
247 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 247 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
248 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 248 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
249 !s101 -O0 249 !s101 -O0
250 !i113 1 250 !i113 1
251 -R4 251 +R5
252 n@m@i@p@s_@pipeline 252 n@m@i@p@s_@pipeline
253 vMIPS_SingleCycle 253 vMIPS_SingleCycle
254 -R5 254 +R7
255 !i10b 1 255 !i10b 1
256 -!s100 dPOY;3F4Z@[X550Mf8=`]2 256 +!s100 Zz<Q962j57a4IzW0mQ=5=1
257 -IQZkQc[MJbHhEVdg`K]7Hm0 257 +IMJcJ>deKe`cm>JGo56D8H2
258 -R0
259 R1 258 R1
260 -w1590757617 259 +R2
260 +w1591531598
261 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 261 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
263 L0 1 263 L0 1
...@@ -265,109 +265,109 @@ R3 ...@@ -265,109 +265,109 @@ R3
265 r1 265 r1
266 !s85 0 266 !s85 0
267 31 267 31
268 -R6 268 +R11
269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
271 !s101 -O0 271 !s101 -O0
272 !i113 1 272 !i113 1
273 -R4 273 +R5
274 n@m@i@p@s_@single@cycle 274 n@m@i@p@s_@single@cycle
275 vMux32bit 275 vMux32bit
276 -R5 276 +R7
277 !i10b 1 277 !i10b 1
278 !s100 foJG^YU75_eND1Og;6Z>O1 278 !s100 foJG^YU75_eND1Og;6Z>O1
279 II3=gjhQD0_cn8mlDL]@bi1 279 II3=gjhQD0_cn8mlDL]@bi1
280 -R0
281 R1 280 R1
282 -Z12 w1590755668 281 +R2
283 -Z13 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 282 +Z14 w1591452448
284 -Z14 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 283 +Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
284 +Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
285 L0 15 285 L0 15
286 R3 286 R3
287 r1 287 r1
288 !s85 0 288 !s85 0
289 31 289 31
290 -R6 290 +R11
291 -Z15 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 291 +Z17 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
292 -Z16 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 292 +Z18 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
293 !s101 -O0 293 !s101 -O0
294 !i113 1 294 !i113 1
295 -R4 295 +R5
296 n@mux32bit 296 n@mux32bit
297 vMux5bit 297 vMux5bit
298 -R5 298 +R7
299 !i10b 1 299 !i10b 1
300 !s100 oSd=[kHDJb<:G7LN4]6@e3 300 !s100 oSd=[kHDJb<:G7LN4]6@e3
301 IfiVXg_aB2GQG7?F@=HcEi0 301 IfiVXg_aB2GQG7?F@=HcEi0
302 -R0
303 R1 302 R1
304 -R12 303 +R2
305 -R13
306 R14 304 R14
305 +R15
306 +R16
307 L0 1 307 L0 1
308 R3 308 R3
309 r1 309 r1
310 !s85 0 310 !s85 0
311 31 311 31
312 -R6 312 +R11
313 -R15 313 +R17
314 -R16 314 +R18
315 !s101 -O0 315 !s101 -O0
316 !i113 1 316 !i113 1
317 -R4 317 +R5
318 n@mux5bit 318 n@mux5bit
319 vMuxBranchSignal 319 vMuxBranchSignal
320 -R5 320 +R7
321 !i10b 1 321 !i10b 1
322 !s100 H1RKS9h`Y6QFX88CRc<g[0 322 !s100 H1RKS9h`Y6QFX88CRc<g[0
323 IGJT?gXMKEEWH?G^lPN79V2 323 IGJT?gXMKEEWH?G^lPN79V2
324 -R0
325 R1 324 R1
326 -R12 325 +R2
327 -R13
328 R14 326 R14
327 +R15
328 +R16
329 L0 29 329 L0 29
330 R3 330 R3
331 r1 331 r1
332 !s85 0 332 !s85 0
333 31 333 31
334 -R6 334 +R11
335 -R15 335 +R17
336 -R16 336 +R18
337 !s101 -O0 337 !s101 -O0
338 !i113 1 338 !i113 1
339 -R4 339 +R5
340 n@mux@branch@signal 340 n@mux@branch@signal
341 vPCcounter 341 vPCcounter
342 -R5 342 +R7
343 !i10b 1 343 !i10b 1
344 -!s100 LU5jEj9S38k[SaIDeL1nG0 344 +!s100 bjm68NMba>Y8oFGU?RHPK0
345 -I81MUZW]CnE2oaQhzNQ:^f3 345 +IU;F]_bg19=g^Z:GGm6U:71
346 -R0
347 R1 346 R1
348 -R7 347 +R2
349 R8 348 R8
350 R9 349 R9
351 -L0 105 350 +R10
351 +L0 198
352 R3 352 R3
353 r1 353 r1
354 !s85 0 354 !s85 0
355 31 355 31
356 -R6
357 -R10
358 R11 356 R11
357 +R12
358 +R13
359 !s101 -O0 359 !s101 -O0
360 !i113 1 360 !i113 1
361 -R4 361 +R5
362 n@p@ccounter 362 n@p@ccounter
363 vRegister 363 vRegister
364 -R5 364 +Z19 !s110 1591621211
365 !i10b 1 365 !i10b 1
366 -!s100 Bdb0dL`fj[<g;4lO0DTA?2 366 +!s100 bC`<7GaPg=bDaZoUR<ADa0
367 -I]1XK2c]z?oKE2lz6^YJ@E2 367 +I<aR5RJ2c1Qba>GdC]KZCd2
368 -R0
369 R1 368 R1
370 R2 369 R2
370 +w1591452599
371 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 371 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
372 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 372 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
373 L0 1 373 L0 1
...@@ -375,21 +375,21 @@ R3 ...@@ -375,21 +375,21 @@ R3
375 r1 375 r1
376 !s85 0 376 !s85 0
377 31 377 31
378 -R6 378 +Z20 !s108 1591621211.000000
379 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 379 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
380 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 380 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
381 !s101 -O0 381 !s101 -O0
382 !i113 1 382 !i113 1
383 -R4 383 +R5
384 n@register 384 n@register
385 vShiftLeft2 385 vShiftLeft2
386 -R5 386 +R19
387 !i10b 1 387 !i10b 1
388 -!s100 eI5Ec:gWMIfN>mTKQIBY93 388 +!s100 ]Zje9D[f?jFRnJBn`OeHc1
389 -I>^Q9<62c;5[Hn[Q?e7H1W0 389 +I]0TYJ]_7?FkOoY=2GlT5=3
390 -R0
391 R1 390 R1
392 R2 391 R2
392 +w1591039219
393 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 393 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
394 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 394 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
395 L0 1 395 L0 1
...@@ -397,21 +397,21 @@ R3 ...@@ -397,21 +397,21 @@ R3
397 r1 397 r1
398 !s85 0 398 !s85 0
399 31 399 31
400 -R6 400 +R20
401 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 401 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
402 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 402 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
403 !s101 -O0 403 !s101 -O0
404 !i113 1 404 !i113 1
405 -R4 405 +R5
406 n@shift@left2 406 n@shift@left2
407 vSignExtend 407 vSignExtend
408 -Z17 !s110 1590758370 408 +R19
409 !i10b 1 409 !i10b 1
410 -!s100 ahVKzC^1fD@70fO3WnVUV0 410 +!s100 =4eXcc0im3]S=Kk@o:eh32
411 -Il`J_9Ud<V7MLm3fGkfTAf0 411 +IFBiMm>fY8WE23A[Ye;CUj3
412 -R0
413 R1 412 R1
414 R2 413 R2
414 +w1591039196
415 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 415 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
416 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 416 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
417 L0 1 417 L0 1
...@@ -419,85 +419,107 @@ R3 ...@@ -419,85 +419,107 @@ R3
419 r1 419 r1
420 !s85 0 420 !s85 0
421 31 421 31
422 -R6 422 +R20
423 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v| 423 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
424 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v| 424 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
425 !s101 -O0 425 !s101 -O0
426 !i113 1 426 !i113 1
427 -R4 427 +R5
428 n@sign@extend 428 n@sign@extend
429 vStall 429 vStall
430 -R5 430 +R19
431 !i10b 1 431 !i10b 1
432 -!s100 DfdOH4n>:HLca08Dem_aV1 432 +!s100 N?ZClBzVEP54JoYb>Ao9:3
433 -IU:EDMN]H5b[DHo4cH[;FR3 433 +I:YbV=h@`DImW@Qc>>HXoc3
434 -R0
435 R1 434 R1
436 -w1590758365 435 +R2
437 -8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 436 +w1591618522
438 -FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 437 +8D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
439 -L0 2 438 +FD:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
439 +L0 1
440 R3 440 R3
441 r1 441 r1
442 !s85 0 442 !s85 0
443 31 443 31
444 -R6 444 +R20
445 -!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v| 445 +!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v|
446 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v| 446 +!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v|
447 !s101 -O0 447 !s101 -O0
448 !i113 1 448 !i113 1
449 -R4 449 +R5
450 n@stall 450 n@stall
451 vtest 451 vtest
452 -R17 452 +Z21 !s110 1591621212
453 !i10b 1 453 !i10b 1
454 -!s100 k>03:b]McFVP5WBB2X74Q1 454 +!s100 KKL;hoG0Ojk_U;6H:]ViZ1
455 -I=8dVVickYZ@kW6ZABDlc_2 455 +Im`S61;3SN3Jlg_1AeFCP@3
456 -R0
457 R1 456 R1
458 -Z18 w1590335687 457 +R2
459 -Z19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v 458 +Z22 w1591501317
460 -Z20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v 459 +Z23 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
460 +Z24 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
461 L0 1 461 L0 1
462 R3 462 R3
463 r1 463 r1
464 !s85 0 464 !s85 0
465 31 465 31
466 -Z21 !s108 1590758370.000000 466 +R20
467 -Z22 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v| 467 +Z25 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
468 -Z23 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v| 468 +Z26 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
469 !s101 -O0 469 !s101 -O0
470 !i113 1 470 !i113 1
471 -R4 471 +R5
472 vtestA 472 vtestA
473 -R17 473 +R21
474 !i10b 1 474 !i10b 1
475 -!s100 N_c21cYjoS9<Wi;WjH:Qc0 475 +!s100 Pkg?M_BZm@c5Y24EY;_H^3
476 -IdN8m[5hjJ3QH?beTSX`:T3 476 +InVhi@1kAoF`f3N_KB]^7i3
477 -R0
478 R1 477 R1
479 -R18 478 +R2
480 -R19 479 +R22
481 -R20 480 +R23
482 -L0 43 481 +R24
482 +L0 24
483 R3 483 R3
484 r1 484 r1
485 !s85 0 485 !s85 0
486 31 486 31
487 +R20
488 +R25
489 +R26
490 +!s101 -O0
491 +!i113 1
492 +R5
493 +ntest@a
494 +vtestB
487 R21 495 R21
496 +!i10b 1
497 +!s100 S@=1_l7e?W`b88GB`bZQS0
498 +Il?;09cMF7Oe7LY1h4do2M3
499 +R1
500 +R2
488 R22 501 R22
489 R23 502 R23
503 +R24
504 +L0 55
505 +R3
506 +r1
507 +!s85 0
508 +31
509 +R20
510 +R25
511 +R26
490 !s101 -O0 512 !s101 -O0
491 !i113 1 513 !i113 1
492 -R4 514 +R5
493 -ntest@a 515 +ntest@b
494 vtestbench 516 vtestbench
495 -R17 517 +!s110 1591621208
496 !i10b 1 518 !i10b 1
497 !s100 OS>9h:91ecFHGVTRNVN]_2 519 !s100 OS>9h:91ecFHGVTRNVN]_2
498 IR?_j2LXMem;jJUiXH@MhI0 520 IR?_j2LXMem;jJUiXH@MhI0
499 -R0
500 R1 521 R1
522 +R2
501 w1590428983 523 w1590428983
502 8D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v 524 8D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
503 FD:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v 525 FD:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
...@@ -506,9 +528,31 @@ R3 ...@@ -506,9 +528,31 @@ R3
506 r1 528 r1
507 !s85 0 529 !s85 0
508 31 530 31
509 -R21 531 +R4
510 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v| 532 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
511 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v| 533 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
512 !s101 -O0 534 !s101 -O0
513 !i113 1 535 !i113 1
514 -R4 536 +R5
537 +vtestPC
538 +R21
539 +!i10b 1
540 +!s100 L_L<o7@FSVAPYd[5blZAI1
541 +I8O06UXYD2fBn2meXg:jBC3
542 +R1
543 +R2
544 +R22
545 +R23
546 +R24
547 +L0 79
548 +R3
549 +r1
550 +!s85 0
551 +31
552 +R20
553 +R25
554 +R26
555 +!s101 -O0
556 +!i113 1
557 +R5
558 +ntest@p@c
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