Single Cycle branch 명령어 몇개 추가 및 pipeline register 추가

@@ -4,14 +4,15 @@ input clk;
 input[31:0] aluin1, aluin2;
 input[31:0] aluin1, aluin2;
 input[3:0] aluctrl;
 input[3:0] aluctrl;
 output reg[31:0] aluout;
 output reg[31:0] aluout;
-output alubranch;
+// output alubranch;
+output reg[5:0] alubranch;
 
 
 reg overflow;
 reg overflow;
 reg[63:0] temp;
 reg[63:0] temp;
 reg[31:0] HI, LO;				// HI, LO register for multiplication and division.
 reg[31:0] HI, LO;				// HI, LO register for multiplication and division.
 reg[31:0] tempHI, tempLO;			// temporary HI, LO register for multiplication and division.
 reg[31:0] tempHI, tempLO;			// temporary HI, LO register for multiplication and division.
 
 
-assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
+// assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
 
 
 initial begin
 initial begin
 	temp = 64'h0000000000000000;
 	temp = 64'h0000000000000000;
@@ -33,6 +34,12 @@ case(aluctrl)
 	4'b0110: begin				// sub
 	4'b0110: begin				// sub
 		aluout = aluin1 - aluin2;
 		aluout = aluin1 - aluin2;
 		overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0;	// overflow detection.
 		overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0;	// overflow detection.
+		alubranch[0] = (aluout == 32'd0) ? 1'b1 : 1'b0;	// beq
+		alubranch[1] = (aluout != 32'd0) ? 1'b1 : 1'b0;	// bne
+		alubranch[2] = (aluin1 > 32'd0) ? 1'b1 : 1'b0;	// bgtz 
+		alubranch[3] = (aluin1 < 32'd0) ? 1'b1 : 1'b0;	// bltz
+		alubranch[4] = (aluin1 >= 32'd0) ? 1'b1 : 1'b0;	// bgez 
+		alubranch[5] = (aluin1 <= 32'd0) ? 1'b1 : 1'b0;	// blez
 	end
 	end
 
 
 	4'b0111: begin				// slt
 	4'b0111: begin				// slt

-module Control(opcode, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
+module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
 
 
 input[5:0] opcode;
 input[5:0] opcode;
+input[4:0] rt;
 input[5:0] funct;
 input[5:0] funct;
-output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, branch, jump,  jumpreg;
+output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump,  jumpreg;
 output reg[3:0] aluctrl;
 output reg[3:0] aluctrl;
+output reg[2:0] branch;
 
 
 always @(*) begin
 always @(*) begin
 	case(opcode)
 	case(opcode)
@@ -14,7 +16,7 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 			memtoreg = 1'b0;
 			memtoreg = 1'b0;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 			case(funct)
 			case(funct)
@@ -41,7 +43,7 @@ always @(*) begin
 					memread = 1'b0;
 					memread = 1'b0;
 					memwrite = 1'b0;
 					memwrite = 1'b0;
 				//	memtoreg = 1'bx;
 				//	memtoreg = 1'bx;
-					branch = 1'b0;
+					branch = 3'b000;
 					jump = 1'b1;
 					jump = 1'b1;
 					jumpreg = 1'b1;
 					jumpreg = 1'b1;
 				end
 				end
@@ -57,7 +59,7 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 			memtoreg = 1'b0;
 			memtoreg = 1'b0;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
@@ -70,7 +72,7 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 			memtoreg = 1'b0;
 			memtoreg = 1'b0;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
@@ -83,20 +85,88 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 			memtoreg = 1'b0;
 			memtoreg = 1'b0;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
 
 
 		6'b000100: begin		// beq instruction
 		6'b000100: begin		// beq instruction
-		//	regdst = 1'bx;	// don't care
+		//	regdst = 1'bx;
+			regwrite = 1'b0;
+			alusrc = 1'b0;
+			aluctrl = 4'b0110;		// sub
+			memread = 1'b0;
+			memwrite = 1'b0;
+		//	memtoreg = 1'bx;
+			branch = 3'b001;
+			jump = 1'b0;
+			jumpreg = 1'b0;
+		end
+
+		6'b000101: begin		// bne instruction
+		//	regdst = 1'bx;
+			regwrite = 1'b0;
+			alusrc = 1'b0;
+			aluctrl = 4'b0110;		// sub
+			memread = 1'b0;
+			memwrite = 1'b0;
+		//	memtoreg = 1'bx;
+			branch = 3'b010;
+			jump = 1'b0;
+			jumpreg = 1'b0;
+		end
+
+		6'b000111: begin		// bgtz instruction
+		//	regdst = 1'bx;
+			regwrite = 1'b0;
+			alusrc = 1'b0;
+			aluctrl = 4'b0110;		// sub
+			memread = 1'b0;
+			memwrite = 1'b0;
+		//	memtoreg = 1'bx;
+			branch = 3'b011;
+			jump = 1'b0;
+			jumpreg = 1'b0;
+		end
+
+		6'b000001: begin
+			case(rt)
+			5'b00000: begin		// bltz instruction
+		//		regdst = 1'bx;
+				regwrite = 1'b0;
+				alusrc = 1'b0;
+				aluctrl = 4'b0110;	// sub
+				memread = 1'b0;
+				memwrite = 1'b0;
+		//		memtoreg = 1'bx;
+				branch = 3'b100;
+				jump = 1'b0;
+				jumpreg = 1'b0;
+			end
+			5'b00001: begin		// bgez instruction
+		//		regdst = 1'bx;
+				regwrite = 1'b0;
+				alusrc = 1'b0;
+				aluctrl = 4'b0110;	// sub
+				memread = 1'b0;
+				memwrite = 1'b0;
+		//		memtoreg = 1'bx;
+				branch = 3'b101;
+				jump = 1'b0;
+				jumpreg = 1'b0;
+			end
+			endcase
+		end
+		
+		6'b000111: begin		// blez instruction
+		//	regdst = 1'bx;
 			regwrite = 1'b0;
 			regwrite = 1'b0;
 			alusrc = 1'b0;
 			alusrc = 1'b0;
 			aluctrl = 4'b0110;		// sub
 			aluctrl = 4'b0110;		// sub
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 		//	memtoreg = 1'bx;
 		//	memtoreg = 1'bx;
-			branch = 1'b1;
+			branch = 3'b110;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
@@ -109,7 +179,7 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 		//	memtoreg = 1'bx;
 		//	memtoreg = 1'bx;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b1;
 			jump = 1'b1;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
@@ -122,7 +192,7 @@ always @(*) begin
 			memread = 1'b1;
 			memread = 1'b1;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 			memtoreg = 1'b1;
 			memtoreg = 1'b1;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
@@ -135,7 +205,7 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b1;
 			memwrite = 1'b1;
 		//	memtoreg = 1'bx;
 		//	memtoreg = 1'bx;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end
@@ -148,7 +218,7 @@ always @(*) begin
 			memread = 1'b0;
 			memread = 1'b0;
 			memwrite = 1'b0;
 			memwrite = 1'b0;
 		//	memtoreg = 1'bx;
 		//	memtoreg = 1'bx;
-			branch = 1'b0;
+			branch = 3'b000;
 			jump = 1'b0;
 			jump = 1'b0;
 			jumpreg = 1'b0;
 			jumpreg = 1'b0;
 		end
 		end

+/* Not Finished */
+module Stall(clk, in_readreg_num1, in_readreg_num2, in_writereg_num);
+
+input clk;
+input[4:0] in_readreg_num1, in_readreg_num2, in_writereg_num;
+
+reg[4:0] writeregs;
+
+endmodule
+
+

+module InstructionMemory(address, instruction);
+
+input[31:0] address;
+output reg[31:0] instruction;
+
+reg[31:0] instr_mem[127:0];
+
+initial begin
+instr_mem[0] = 32'd0;
+instr_mem[1] = 32'b00100100000010000000000011111111;		// addi, $0 $8 255
+instr_mem[2] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
+instr_mem[3] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
+instr_mem[4] = 32'b00010001000010100000000000000001;		// beq, $8 $10 +1
+instr_mem[5] = 32'd0;
+instr_mem[6] = 32'b00000001000010010000000000011000;		// mult, $8 $9
+instr_mem[7] = 32'd0;
+instr_mem[8] = 32'b00000000000000000110000000010000;		// mfhi, $12
+instr_mem[9] = 32'b00000000000000000110100000010010;		// mflo, $13
+instr_mem[10] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
+instr_mem[11] = 32'd0;
+instr_mem[12] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
+instr_mem[13] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
+instr_mem[14] = 32'd0;
+instr_mem[15] = 32'b00000000000000000000000000001000;		// jr, $0
+
+end
+
+always @ (*) begin
+	instruction = instr_mem[address/4];
+end
+
+endmodule

+D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module testbench
+
+Top level modules:
+	testbench
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module test
+-- Compiling module testA
+
+Top level modules:
+	test
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Adder
+
+Top level modules:
+	Adder
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module MIPS_SingleCycle
+
+Top level modules:
+	MIPS_SingleCycle
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module InstructionMemory
+
+Top level modules:
+	InstructionMemory
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Register
+
+Top level modules:
+	Register
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module IF_ID
+-- Compiling module ID_EX
+-- Compiling module EX_MEM
+-- Compiling module MEM_WB
+-- Compiling module PCcounter
+
+Top level modules:
+	IF_ID
+	ID_EX
+	EX_MEM
+	MEM_WB
+	PCcounter
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module MIPS_Pipeline
+
+Top level modules:
+	MIPS_Pipeline
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Stall
+
+Top level modules:
+	Stall
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module SignExtend
+
+Top level modules:
+	SignExtend
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Control
+
+Top level modules:
+	Control
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Mux5bit
+-- Compiling module Mux32bit
+-- Compiling module MuxBranchSignal
+
+Top level modules:
+	Mux5bit
+	Mux32bit
+	MuxBranchSignal
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module ALU
+
+Top level modules:
+	ALU
+
+} {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module DataMemory
+
+Top level modules:
+	DataMemory
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module ShiftLeft2
+
+Top level modules:
+	ShiftLeft2
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module Clock
+
+Top level modules:
+	Clock
+
+} {} {}}

@@ -816,7 +816,7 @@ Resolution = ns
 UserTimeUnit = default
 UserTimeUnit = default
 
 
 ; Default run length
 ; Default run length
-RunLength = 100 ns
+RunLength = 100
 
 
 ; Maximum iterations that can be run without advancing simulation time
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 10000000
 IterationLimit = 10000000
@@ -2034,27 +2034,39 @@ suppress = 8780 ;an explanation can be had by running: verror 8780
 Project_Version = 6
 Project_Version = 6
 Project_DefaultLib = work
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_SortMethod = unused
-Project_Files_Count = 10
-Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590179259 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1589586193 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590180454 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1589585780 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1589585757 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590179680 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590176245 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590177608 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1589586199 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590179297 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Files_Count = 16
+Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590428983 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590335687 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757617 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757768 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757593 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1590758341 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1590758365 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590757464 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590755668 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590755442 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1590245372 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
 Echo_Compile_Output = 0

+// Test Required
+module MIPS_Pipeline;
+
+wire clk;							// clock
+wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		
+
+wire[31:0] instr;						// loaded instruction.
+
+wire[4:0] reg_writereg1;					// register number for the write data.
+wire[31:0] reg_writedata;					// data that will be written in the register.
+wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.
+
+wire[31:0] alu_input2;						// input data of ALU.
+wire[31:0] alu_result;						// result data of ALU.
+wire[5:0] alu_branch;						// indicator for branch operation.
+
+wire[31:0] mem_readdata;					// data from the requested address.
+
+wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
+wire[3:0] ctrl_aluctrl;						// control signals.
+wire[2:0] ctrl_branch;
+
+wire[31:0] extend_output;
+
+wire[31:0] shiftBranch_output;
+wire[31:0] shiftJump_output;
+
+// IF_ID register outputs
+wire[31:0] ifid_instr, ifid_PC_4;
+
+// ID_EX register outputs
+wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
+wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg;
+wire[3:0] idex_aluctrl; 
+wire[2:0] idex_branch;
+wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;
+
+// EX_MEM register outputs
+wire[4:0] exmem_writereg1;
+wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump;
+wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;
+
+// MEM_WB register outputs
+wire[4:0] memwb_writereg1;
+wire memwb_regwrite, memwb_memtoreg, memwb_jump;
+wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;
+
+
+Clock clock(clk);
+PCcounter pccounter(clk, nextPC, instr_address);
+
+// Instruction Fetch
+InstructionMemory instrmem(instr_address, instr);
+Adder add_pc4(PC, 32'h00000004, addPC4);
+
+IF_ID ifid(clk, instr, addPC4, 
+	ifid_instr, ifid_PC_4);
+
+// Instruction Decode
+Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
+Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11],  ctrl_regdst,  reg_writereg1);
+Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata,  memwb_regwrite,  reg_readdata1, reg_readdata2);
+SignExtend extend(ifid_instr[15:0], extend_output);
+ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
+
+ID_EX idex(clk, reg_writereg1, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 
+	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, ifid_instr[25:21], ifid_instr[20:16], 
+	idex_writereg1, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 
+	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump, idex_readreg_num1, idex_readreg_num2);
+
+// Execute
+Mux32bit mux_alusrc(idex_readdata2, idex_extend,  idex_alusrc,  alu_input2);
+ALU alu(clk, idex_readdata1, alu_input2,  idex_aluctrl,  alu_result, alu_branch);
+ShiftLeft2 shiftBranch(idex_extend, shiftBranch_output);
+Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
+MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
+Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);
+
+EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, 
+	alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 
+	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, 
+	exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
+
+// Memory
+DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exmem_memwrite,  mem_readdata);
+Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch,  exmem_branch ,  tempPC_branch);
+
+MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 
+	exmem_aluresult, mem_readdata, tempPC_branch, exmem_PCjump, 
+	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 
+	memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump);
+
+// Writeback
+Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  reg_writedata);
+Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump,  memwb_jump,  nextPC);
+
+
+
+
+always @(posedge clk) begin
+
+end
+
+/*
+wire clk;							// clock
+reg[31:0] PC, instr_address;
+
+// IF - ID
+wire[31:0] if_id_instruction, if_id_pc_4;
+
+// ID - EX
+wire[31:0] id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump;
+wire[4:0] id_ex_writereg, id_hh_readreg1, id_hh_readreg2;
+wire id_ex_regwrite, id_ex_alusrc, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg;
+wire[3:0] id_ex_aluctrl;
+
+// EX - MEM
+wire[31:0] ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch;
+wire[4:0] ex_mem_writereg;
+wire ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump;
+
+// MEM - WB
+wire[4:0] mem_wb_writereg_num;
+wire mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump;
+wire[31:0] mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump;
+
+// WB - etc.
+wire wb_id_regwrite;
+wire[4:0] wb_id_writereg;
+wire[31:0] wb_id_reg_writedata;
+wire[31:0] wb_nextPC;
+
+Clock clock(clk);
+
+InstructionFetch IF(clk, PC,  if_id_instruction, if_id_pc_4);
+
+InstructionDecode ID(clk, if_id_instruction, if_id_pc_4, wb_id_writereg, wb_id_reg_writedata, wb_id_regwrite, 
+	id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
+	id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump);
+
+Execute EX(clk, id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
+	id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump, 
+	ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump, 
+	ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch);
+
+Mem MEM(clk, ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump, 
+	ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch, 
+	mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump);
+
+WriteBack WB(clk, mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump, 
+	wb_id_regwrite, wb_id_writereg, wb_id_reg_writedata, wb_nextPC);
+
+initial begin
+	PC = 32'hfffffffc;
+end
+
+always @(posedge clk) begin
+	instr_address = PC;
+end
+
+always @(negedge clk) begin
+	PC = PC + 4;
+end
+*/
+endmodule

+module MIPS_SingleCycle;
+
+wire clk;							// clock
+reg[31:0] PC;							// program counter
+reg[31:0] instr_address;
+wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		
+
+wire[31:0] instr;						// loaded instruction.
+
+wire[4:0] reg_writereg1;					// register number for the write data.
+wire[31:0] reg_writedata;					// data that will be written in the register.
+wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.
+
+wire[31:0] alu_input2;						// input data of ALU.
+wire[31:0] alu_result;						// result data of ALU.
+wire[5:0] alu_branch;						// indicator for branch operation.
+
+wire[31:0] mem_readdata;					// data from the requested address.
+
+wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
+wire[3:0] ctrl_aluctrl;
+wire[2:0] ctrl_branch;						// control signals.
+
+wire[31:0] extend_output;
+
+wire[31:0] shiftBranch_output;
+wire[31:0] shiftJump_output;
+
+Clock clock(clk);
+InstructionMemory instrmem(instr_address, instr);
+Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata,  ctrl_regwrite,  reg_readdata1, reg_readdata2);
+ALU alu(clk, reg_readdata1, alu_input2,  ctrl_aluctrl,  alu_result, alu_branch);
+DataMemory datamem(clk, alu_result, reg_readdata2,  ctrl_memread, ctrl_memwrite,  mem_readdata);
+Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
+Mux5bit mux_regdst(instr[20:16], instr[15:11],  ctrl_regdst,  reg_writereg1);
+MuxBranchSignal mux_branchsignal(alu_branch,  ctrl_branch,  branch_signal);
+Mux32bit mux_alusrc(reg_readdata2, extend_output,  ctrl_alusrc,  alu_input2);
+Mux32bit mux_memtoreg(alu_result, mem_readdata,  ctrl_memtoreg,  reg_writedata);
+Mux32bit mux_branch(addPC4, addPCbranch,  branch_signal ,  tempPC_branch);
+Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1,  ctrl_jumpreg,  tempPC_jump);
+Mux32bit mux_jump(tempPC_branch, tempPC_jump,  ctrl_jump,  nextPC);
+SignExtend extend(instr[15:0], extend_output);
+Adder add_pc4(PC, 32'h00000004, addPC4);
+Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
+ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
+ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
+
+initial begin
+	PC = 32'h00000000;
+end
+
+always @(posedge clk) begin
+	case(nextPC[31])					// if nextPC is available, PC = nextPC.
+		1'b0: PC = nextPC;
+		1'b1: PC = nextPC;
+	endcase
+
+	instr_address = PC;
+end
+
+endmodule

 module Mux5bit(input1, input2, signal, output1);
 module Mux5bit(input1, input2, signal, output1);
-
 input[4:0] input1, input2;
 input[4:0] input1, input2;
 input signal;
 input signal;
 output reg[4:0] output1;
 output reg[4:0] output1;
@@ -10,11 +9,10 @@ always @(*) begin
 		1'b1: output1 = input2;
 		1'b1: output1 = input2;
 	endcase
 	endcase
 end
 end
-
 endmodule
 endmodule
 
 
-module Mux32bit(input1, input2, signal, output1);
 
 
+module Mux32bit(input1, input2, signal, output1);
 input[31:0] input1, input2;
 input[31:0] input1, input2;
 input signal;
 input signal;
 output reg[31:0] output1;
 output reg[31:0] output1;
@@ -25,5 +23,24 @@ always @(*) begin
 		1'b1: output1 = input2;
 		1'b1: output1 = input2;
 	endcase
 	endcase
 end
 end
+endmodule
+
+
+module MuxBranchSignal(input1, signal, output1);
+input[5:0] input1;
+input[2:0] signal;
+output reg output1;
+
+always @(*) begin
+	case(signal)
+		3'b000: output1 = 1'b0;
+		3'b001: output1 = input1[0];
+		3'b010: output1 = input1[1];
+		3'b011: output1 = input1[2];
+		3'b100: output1 = input1[3];
+		3'b101: output1 = input1[4];
+		3'b110: output1 = input1[5];
+	endcase
+end
 
 
 endmodule
 endmodule

+module IF_ID(clk, in_instruction, in_PC_4, 
+	out_instruction, out_PC_4);
+input clk;
+input[31:0] in_instruction, in_PC_4;
+output reg[31:0] out_instruction, out_PC_4;
+
+always @(posedge clk) begin
+	out_instruction <= in_instruction;
+	out_PC_4 <= in_PC_4;
+end
+endmodule
+
+
+module ID_EX(clk, in_writereg_num, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 
+	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2, 
+	out_writereg_num, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 
+	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2);
+input clk;
+input[4:0] in_writereg_num;
+input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg;
+input[3:0] in_aluctrl;
+input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2;
+output reg[4:0] out_writereg_num;
+output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg;
+output reg[3:0] out_aluctrl;
+output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2;
+
+always @(posedge clk) begin
+	out_writereg_num <= in_writereg_num;
+	out_regwrite <= in_regwrite;
+	out_alusrc <= in_alusrc;
+	out_aluctrl <= in_aluctrl;
+	out_memread <= in_memread;
+	out_memwrite <= in_memwrite;
+	out_memtoreg <= in_memtoreg;
+	out_branch <= in_branch;
+	out_jump <= in_jump;
+	out_jumpreg <= in_jumpreg;
+
+	out_readdata1 <= in_readdata1;
+	out_readdata2 <= in_readdata2;
+	out_extenddata <= in_extenddata;
+	out_PC_4 <= out_PC_4;
+	out_tempPCjump <= in_tempPCjump;
+	out_readreg_num1 <= in_readreg_num1;
+	out_readreg_num2 <= in_readreg_num2;
+end
+endmodule
+
+
+module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, 
+	in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 
+	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 
+	out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
+input clk;
+input[4:0] in_writereg_num;
+input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
+input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
+output reg[4:0] out_writereg_num;
+output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump;
+output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;
+
+always @(posedge clk) begin
+	out_writereg_num <= in_writereg_num;
+	out_regwrite <= in_regwrite;
+	out_memread <= in_memread;
+	out_memwrite <= in_memwrite;
+	out_memtoreg <= in_memtoreg;
+	out_branch <= in_branch;
+	out_jump <= in_jump;
+
+	out_aluresult <= in_aluresult;
+	out_mem_writedata <= in_mem_writedata;
+	out_PC_4 <= in_PC_4;
+	out_PCjump <= in_PCjump;
+	out_tempPCbranch <= in_tempPCbranch;
+end
+endmodule
+
+
+module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 
+	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCbranch, out_PCjump);
+input clk;
+input[4:0] in_writereg_num;
+input in_regwrite, in_memtoreg, in_jump;
+input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
+output reg[4:0] out_writereg_num;
+output reg out_regwrite, out_memtoreg, out_jump;
+output reg[31:0] out_aluresult, out_memreaddata, out_PCbranch, out_PCjump;
+
+always @(posedge clk) begin
+	out_writereg_num <= in_writereg_num;
+	out_regwrite <= in_regwrite;
+	out_memtoreg <= in_memtoreg;
+	out_jump <= in_jump;
+
+	out_aluresult <= in_aluresult;
+	out_memreaddata <= in_memreaddata;
+	out_PCbranch <= out_PCbranch;
+	out_PCjump <= out_PCjump;
+end
+endmodule
+
+/* Not Finished */
+module PCcounter(clk, in_pc, out_nextpc);
+input clk;
+input[31:0] in_pc;
+output reg[31:0] out_nextpc;
+reg[31:0] PC;
+
+initial begin
+	PC = 32'h00000000;
+end
+
+always @(posedge clk) begin
+/*
+	case(in_pc[31])					// if in_pc is available, PC = in_pc.
+		1'b0: PC = in_pc;
+		1'b1: PC = in_pc;
+	endcase
+*/
+	PC <= PC+4;
+	out_nextpc <= PC;
+end
+
+endmodule

+module test;
+
+wire clk;
+reg sig1;
+reg[31:0] in1;
+wire[31:0] out1, out2;
+
+Clock clock(clk);
+testA ta(clk, sig1, in1, out1, out2);
+
+initial begin
+	sig1 <= 1'b0;
+	in1 <= 32'd0;
+	#100;
+	in1 <= 32'hffffffff;
+	#100;
+	sig1 <= 1'b1;
+	in1 <= 32'h0000ffff; 
+	#100;
+	sig1 <= 1'b1;
+	in1 <= 32'hffff0000; 
+	#100;
+end
+
+/*
+wire clk;
+reg[31:0] pc;
+wire[31:0] instr, tempPC;
+
+Clock clock(clk);
+InstructionFetch IF(clk, pc, instr, tempPC);
+
+initial begin
+	pc = 32'hfffffffc;
+end
+
+always @(negedge clk) begin
+	pc = pc + 4;
+end
+*/
+endmodule
+
+module testA(clk, sig1, in1, out1, out2);
+
+input clk, sig1;
+input[31:0] in1;
+output reg[31:0] out1, out2;
+
+always @(posedge clk) begin
+	out1 <= in1;
+	if(sig1 == 1) out2 <= in1;
+end
+
+endmodule

@@ -31,9 +31,9 @@ Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata,
 ALU alu(clk, reg_readdata1, alu_input2,  ctrl_aluctrl,  alu_result, alu_branch);
 ALU alu(clk, reg_readdata1, alu_input2,  ctrl_aluctrl,  alu_result, alu_branch);
 DataMemory datamem(clk, alu_result, reg_readdata2,  ctrl_memread, ctrl_memwrite,  mem_readdata);
 DataMemory datamem(clk, alu_result, reg_readdata2,  ctrl_memread, ctrl_memwrite,  mem_readdata);
 Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
 Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
-Mux5bit mux_writereg(instr[20:16], instr[15:11],  ctrl_regdst,  reg_writereg1);
-Mux32bit mux_alu(reg_readdata2, extend_output,  ctrl_alusrc,  alu_input2);
-Mux32bit mux_writedata(alu_result, mem_readdata,  ctrl_memtoreg,  reg_writedata);
+Mux5bit mux_regdst(instr[20:16], instr[15:11],  ctrl_regdst,  reg_writereg1);
+Mux32bit mux_alusrc(reg_readdata2, extend_output,  ctrl_alusrc,  alu_input2);
+Mux32bit mux_memtoreg(alu_result, mem_readdata,  ctrl_memtoreg,  reg_writedata);
 Mux32bit mux_branch(addPC4, addPCbranch,  {ctrl_branch&alu_branch} ,  tempPC_branch);
 Mux32bit mux_branch(addPC4, addPCbranch,  {ctrl_branch&alu_branch} ,  tempPC_branch);
 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1,  ctrl_jumpreg,  tempPC_jump);
 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1,  ctrl_jumpreg,  tempPC_jump);
 Mux32bit mux_jump(tempPC_branch, tempPC_jump,  ctrl_jump,  nextPC);
 Mux32bit mux_jump(tempPC_branch, tempPC_jump,  ctrl_jump,  nextPC);

+m255
+K4
+z2
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+dD:/class/Capstone1/KNW_Project2/Project/Pipeline
+vAdder
+!s110 1590758368
+!i10b 1
+!s100 C]ac0M5ljAN8jKk:YMWUe1
+IDi2UW;IAjgeEI=Re1d6>j0
+Z0 VDg1SIo80bB@j0V0VzS_@n1
+Z1 dD:/class/Capstone1/KNW_Project2/Project/MIPS
+Z2 w1590245372
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
+L0 1
+Z3 OP;L;10.4a;61
+r1
+!s85 0
+31
+!s108 1590758368.000000
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
+!s101 -O0
+!i113 1
+Z4 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
+n@adder
+vALU
+Z5 !s110 1590758369
+!i10b 1
+!s100 8`_QAORX^JgbcU:FJndD:1
+I^ma26jUAmP4?NRZPY^4G=2
+R0
+R1
+w1590755442
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+L0 1
+R3
+r1
+!s85 0
+31
+Z6 !s108 1590758369.000000
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
+!s101 -O0
+!i113 1
+R4
+n@a@l@u
+vClock
+R5
+!i10b 1
+!s100 OWQXV6kDYiT>ChTOoCFa]2
+IQHn8SmB<S>;8X8GE^RU_a0
+R0
+R1
+R2
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
+!s101 -O0
+!i113 1
+R4
+n@clock
+vControl
+R5
+!i10b 1
+!s100 RnD5[K2b[j8<X09[R7]kZ2
+I_4RCzG]R_IOaidB1NCK7D0
+R0
+R1
+w1590757464
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
+!s101 -O0
+!i113 1
+R4
+n@control
+vDataMemory
+R5
+!i10b 1
+!s100 RT9n9HH7ShGYTRk0Zj<MK3
+IbciGN62QS2]SHi<BkL<2=2
+R0
+R1
+R2
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
+!s101 -O0
+!i113 1
+R4
+n@data@memory
+vEX_MEM
+R5
+!i10b 1
+!s100 ]8:X<?W@7Q@:C>XWDd6?W2
+ISC6^?55L`OXYAVlPjf`nE1
+R0
+R1
+Z7 w1590758341
+Z8 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+Z9 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+L0 51
+R3
+r1
+!s85 0
+31
+R6
+Z10 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z11 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+!s101 -O0
+!i113 1
+R4
+n@e@x_@m@e@m
+vID_EX
+R5
+!i10b 1
+!s100 AOa7M@:@;]1<l5@<:]DoZ3
+I1^7Xh>glK<B3GFZz?nHKG1
+R0
+R1
+R7
+R8
+R9
+L0 14
+R3
+r1
+!s85 0
+31
+R6
+R10
+R11
+!s101 -O0
+!i113 1
+R4
+n@i@d_@e@x
+vIF_ID
+R5
+!i10b 1
+!s100 gnf82IK;Q2HN9lh8hggGU3
+I;=kYGK18[WJPiNhbdWnK>2
+R0
+R1
+R7
+R8
+R9
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+R10
+R11
+!s101 -O0
+!i113 1
+R4
+n@i@f_@i@d
+vInstructionMemory
+R5
+!i10b 1
+!s100 6FSBo3he?<YZH8SWT@?520
+I[UoXc[5<F^Vo]d2STIEaL3
+R0
+R1
+w1590757768
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
+!s101 -O0
+!i113 1
+R4
+n@instruction@memory
+vMEM_WB
+R5
+!i10b 1
+!s100 U4fQaKDggSoeYLh<eCFgU0
+I@gj2Xh:PnQJOY356SH^a`2
+R0
+R1
+R7
+R8
+R9
+L0 81
+R3
+r1
+!s85 0
+31
+R6
+R10
+R11
+!s101 -O0
+!i113 1
+R4
+n@m@e@m_@w@b
+vMIPS_Pipeline
+R5
+!i10b 1
+!s100 d<3zzA7z4RnP`AU2`TaFC3
+Iao5jbloRQ>=BcXMPeBS3V0
+R0
+R1
+w1590757593
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+L0 2
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
+!s101 -O0
+!i113 1
+R4
+n@m@i@p@s_@pipeline
+vMIPS_SingleCycle
+R5
+!i10b 1
+!s100 dPOY;3F4Z@[X550Mf8=`]2
+IQZkQc[MJbHhEVdg`K]7Hm0
+R0
+R1
+w1590757617
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
+!s101 -O0
+!i113 1
+R4
+n@m@i@p@s_@single@cycle
+vMux32bit
+R5
+!i10b 1
+!s100 foJG^YU75_eND1Og;6Z>O1
+II3=gjhQD0_cn8mlDL]@bi1
+R0
+R1
+Z12 w1590755668
+Z13 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Z14 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+L0 15
+R3
+r1
+!s85 0
+31
+R6
+Z15 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+Z16 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+!s101 -O0
+!i113 1
+R4
+n@mux32bit
+vMux5bit
+R5
+!i10b 1
+!s100 oSd=[kHDJb<:G7LN4]6@e3
+IfiVXg_aB2GQG7?F@=HcEi0
+R0
+R1
+R12
+R13
+R14
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+R15
+R16
+!s101 -O0
+!i113 1
+R4
+n@mux5bit
+vMuxBranchSignal
+R5
+!i10b 1
+!s100 H1RKS9h`Y6QFX88CRc<g[0
+IGJT?gXMKEEWH?G^lPN79V2
+R0
+R1
+R12
+R13
+R14
+L0 29
+R3
+r1
+!s85 0
+31
+R6
+R15
+R16
+!s101 -O0
+!i113 1
+R4
+n@mux@branch@signal
+vPCcounter
+R5
+!i10b 1
+!s100 LU5jEj9S38k[SaIDeL1nG0
+I81MUZW]CnE2oaQhzNQ:^f3
+R0
+R1
+R7
+R8
+R9
+L0 105
+R3
+r1
+!s85 0
+31
+R6
+R10
+R11
+!s101 -O0
+!i113 1
+R4
+n@p@ccounter
+vRegister
+R5
+!i10b 1
+!s100 Bdb0dL`fj[<g;4lO0DTA?2
+I]1XK2c]z?oKE2lz6^YJ@E2
+R0
+R1
+R2
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
+!s101 -O0
+!i113 1
+R4
+n@register
+vShiftLeft2
+R5
+!i10b 1
+!s100 eI5Ec:gWMIfN>mTKQIBY93
+I>^Q9<62c;5[Hn[Q?e7H1W0
+R0
+R1
+R2
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
+!s101 -O0
+!i113 1
+R4
+n@shift@left2
+vSignExtend
+Z17 !s110 1590758370
+!i10b 1
+!s100 ahVKzC^1fD@70fO3WnVUV0
+Il`J_9Ud<V7MLm3fGkfTAf0
+R0
+R1
+R2
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
+L0 1
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
+!s101 -O0
+!i113 1
+R4
+n@sign@extend
+vStall
+R5
+!i10b 1
+!s100 DfdOH4n>:HLca08Dem_aV1
+IU:EDMN]H5b[DHo4cH[;FR3
+R0
+R1
+w1590758365
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+L0 2
+R3
+r1
+!s85 0
+31
+R6
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+!s101 -O0
+!i113 1
+R4
+n@stall
+vtest
+R17
+!i10b 1
+!s100 k>03:b]McFVP5WBB2X74Q1
+I=8dVVickYZ@kW6ZABDlc_2
+R0
+R1
+Z18 w1590335687
+Z19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+Z20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
+L0 1
+R3
+r1
+!s85 0
+31
+Z21 !s108 1590758370.000000
+Z22 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
+Z23 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
+!s101 -O0
+!i113 1
+R4
+vtestA
+R17
+!i10b 1
+!s100 N_c21cYjoS9<Wi;WjH:Qc0
+IdN8m[5hjJ3QH?beTSX`:T3
+R0
+R1
+R18
+R19
+R20
+L0 43
+R3
+r1
+!s85 0
+31
+R21
+R22
+R23
+!s101 -O0
+!i113 1
+R4
+ntest@a
+vtestbench
+R17
+!i10b 1
+!s100 OS>9h:91ecFHGVTRNVN]_2
+IR?_j2LXMem;jJUiXH@MhI0
+R0
+R1
+w1590428983
+8D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
+FD:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
+L0 1
+R3
+r1
+!s85 0
+31
+R21
+!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
+!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
+!s101 -O0
+!i113 1
+R4

-module InstructionMemory(address, instruction);
-
-input[31:0] address;
-output reg[31:0] instruction;
-
-reg[31:0] instr_mem[127:0];
-
-initial begin
-instr_mem[0] = 32'd0;
-instr_mem[1] = 32'b00100100000010000000000011111111;		// addi $0 $8 255
-instr_mem[2] = 32'b00000001000010000100100000100000;		// add $8 $8 $9
-instr_mem[3] = 32'b00000001000000000101000000100000;		// add $8 $0 $10
-instr_mem[4] = 32'b00010001000010110000000000000001;		// beq $8 $11 +1
-instr_mem[5] = 32'b00000001000010010000000000011000;		// mult $8 $9
-instr_mem[6] = 32'd0;
-instr_mem[7] = 32'b00000000000000000110000000010000;		// mfhi $12
-instr_mem[8] = 32'b00000000000000000110100000010010;		// mflo $13
-instr_mem[9] = 32'b10101100000011010000000000111100;		// sw $0 $13 60
-instr_mem[10] = 32'd0;
-instr_mem[11] = 32'b00010001000010110000000000000001;		// beq $8 $11 +1
-instr_mem[12] = 32'b10001100000000010000000000111100;		// lw $0 $1 60
-instr_mem[13] = 32'd0;
-instr_mem[14] = 32'b00000000000000000000000000001000;		// jr $0
-
-
-
-end
-
-always @ (*) begin
-	instruction = instr_mem[address/4];
-end
-
-endmodule

-D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module ShiftLeft2
-
-Top level modules:
-	ShiftLeft2
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module InstructionMemory
-
-Top level modules:
-	InstructionMemory
-
-} {} {}} {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v}
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module DataMemory
-
-Top level modules:
-	DataMemory
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module testbench
-
-Top level modules:
-	testbench
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module Clock
-
-Top level modules:
-	Clock
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module Adder
-
-Top level modules:
-	Adder
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module SignExtend
-
-Top level modules:
-	SignExtend
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module Register
-
-Top level modules:
-	Register
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module Control
-
-Top level modules:
-	Control
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module ALU
-
-Top level modules:
-	ALU
-
-} {} {}}

-module test;
-
-reg[31:0] in1, in2;
-reg[3:0] ctrl;
-wire[31:0] out;
-wire a;
-
-ALU alu(in1, in2, ctrl, out, a);
-
-initial begin
-	in1 = 32'd128;
-	in2 = 32'd982;
-	ctrl = 4'b1000;
-	#100;
-	in1 = 32'd123;
-	in2 = 32'd246;
-	ctrl = 4'b0010;
-	#100;
-	ctrl = 4'b1010;
-	#100;
-	ctrl = 4'b1011;
-	#100;
-end
-
-/*
-wire clk;
-
-Clock clock(clk);
-*/
-
-/*
-reg[31:0] address, wdata;
-reg mr, mw;
-wire[31:0] rdata;
-
-DataMemory damem(address, wdata, mr, mw, rdata);
-
-initial begin
-	address = 32'd0;
-	wdata = 32'd127;
-	mr = 1'b0;
-	mw = 1'b1;
-	#100;
-	address = 32'd48;
-	wdata = 32'd255;
-	mr = 1'b0;
-	mw = 1'b1;
-	#100;
-	address = 32'd48;
-	wdata = 32'd255;
-	mr = 1'b1;
-	mw = 1'b0;
-	#100;
-	address = 32'd48;
-	wdata = 32'd4;
-	mr = 1'b0;
-	mw = 1'b1;
-	#100;
-end
-*/
-
-/*
-wire[31:0] regout1, regout2;
-reg[4:0] ins1, ins2, ins3;
-wire[31:0] aluresult;
-reg[3:0] aluctrl;
-reg rwrite;
-reg[31:0] aluin2;
-
-Register Regi(ins1, ins2, ins3, aluresult, rwrite, regout1, regout2);
-ALU alu(regout1, aluin2, aluctrl, aluresult);
-
-initial begin
-	rwrite = 1;
-	ins1 = 5'd0;
-	ins2 = 5'd29;
-	ins3 = 5'd7;
-	aluin2 = 32'h7fffffff;
-	aluctrl = 4'b0010;
-	#100;
-	rwrite = 1;
-	ins1 = 5'd7;
-	ins2 = 5'd7;
-	ins3 = 5'd8;
-	aluctrl = 4'b0010;
-	#100;
-	rwrite = 0;
-	#100;
-	rwrite = 1;
-	ins1 = 5'd0;
-	ins2 = 5'd29;
-	ins3 = 5'd7;
-	aluin2 = 32'h7fffffff;
-	aluctrl = 4'b0010;
-	#100;
-	rwrite = 1;
-	ins1 = 5'd7;
-	ins2 = 5'd7;
-	ins3 = 5'd8;
-	aluctrl = 4'b0010;
-	#100;
-end
-*/
-
-/*
-reg[31:0] input1, input2;
-reg[3:0] ctrl;
-wire[31:0] output1;
-wire zero;
-
-ALU testalu(input1, input2, ctrl, output1, zero);
-
-initial begin
-	input1 <= 32'h0000000f;
-	input2 <= 32'h000000f0;
-	ctrl <=  4'h0;	// add
-	#100;
-	ctrl <= 4'h1;	// or
-	#100;
-	ctrl <= 4'h2;	// add
-	#100;
-	ctrl <= 4'h6;	// sub
-	#100;
-	ctrl <= 4'h7;	// slt
-	#100;
-	ctrl <= 4'hc;	// nor
-	#100;
-	input1 <= 32'h000000f0;
-	input2 <= 32'h0000000f;
-	ctrl <= 4'h6;	// sub
-	#100;
-	input1 <= 32'h000000f0;
-	input2 <= 32'h0000000f;
-	ctrl <= 4'h6;	// sub
-	#100;
-	input1 <= 32'h000000f0;
-	input2 <= 32'h0000000f;
-	ctrl <= 4'h6;	// sub
-	#100;
-	input1 <= 32'h000000f0;
-	input2 <= 32'h0000000f;
-	ctrl <= 4'h6;	// sub
-	#100;
-end
-*/
-
-/*
-reg[31:0] input1;
-wire[31:0] output1;
-
-InstructionMemory im(input1, output1);
-
-initial
-begin
-	input1 = {{28{1'b0}}, 4'b0000};
-	#100;
-	input1 = {{28{1'b0}}, 4'b1100};
-	#100;
-	input1 = {{28{1'b0}}, 4'b1000};
-	#100;
-	input1 = {{28{1'b0}}, 4'b0100};
-	#100;
-	input1 = {{28{1'b0}}, 4'b0000};
-	#100;
-end
-*/
-
-/*
-reg[7:0] input1;
-wire[7:0] output1;
-
-Adder adder1(input1, 8'b00000001, output1);
-
-initial
-begin
-	input1 = 8'b00001111;
-	#100;
-	input1 = 8'b00001000;
-	#100;
-	input1 = 8'b00000000;
-	#100;
-	input1 = 8'b11111111;
-	#100;
-end
-*/
-endmodule

-m255
-K4
-z2
-13
-!s112 1.1
-!i10d 8192
-!i10e 25
-!i10f 100
-cModel Technology
-dC:/Modeltech_pe_edu_10.4a/examples
-vAdder
-Z0 !s110 1590181223
-!i10b 1
-!s100 C]ac0M5ljAN8jKk:YMWUe1
-IPABU2L8BVV2T>WDY4a1F@3
-Z1 VDg1SIo80bB@j0V0VzS_@n1
-Z2 dD:/class/Capstone1/KNW_Project2/Project/SingleCycle
-w1589585757
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
-L0 1
-Z3 OP;L;10.4a;61
-r1
-!s85 0
-31
-Z4 !s108 1590181223.000000
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v|
-!s101 -O0
-!i113 1
-Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
-n@adder
-vALU
-R0
-!i10b 1
-!s100 :;Xi4U9^j:B2YKA2g;48a2
-Ilz@oO[_i9<DDh^X5Z@MYO2
-R1
-R2
-w1590179297
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
-L0 1
-R3
-r1
-!s85 0
-31
-R4
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v|
-!s101 -O0
-!i113 1
-R5
-n@a@l@u
-vALUControl
-Z6 !s110 1590134077
-!i10b 1
-!s100 5M;8KH=?8dC:nP8HEC8AT0
-Ij7f_HKS32W^mlmZIBXe=P0
-R1
-R2
-w1589611047
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v
-L0 1
-R3
-r1
-!s85 0
-31
-Z7 !s108 1590134077.000000
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU_Control.v|
-!s101 -O0
-!i113 1
-R5
-n@a@l@u@control
-vClock
-Z8 !s110 1590181224
-!i10b 1
-!s100 OWQXV6kDYiT>ChTOoCFa]2
-IQ3e7_okQ4UFF5[gGVRJ]L2
-R1
-R2
-w1589585780
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
-L0 1
-R3
-r1
-!s85 0
-31
-Z9 !s108 1590181224.000000
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v|
-!s101 -O0
-!i113 1
-R5
-n@clock
-vControl
-R8
-!i10b 1
-!s100 h4IKEzP5K:837Y_KUcOW]0
-I3T=^6M9lNafR2XL8nj12I1
-R1
-R2
-w1590177608
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
-L0 1
-R3
-r1
-!s85 0
-31
-R9
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v|
-!s101 -O0
-!i113 1
-R5
-n@control
-vDataMemory
-R8
-!i10b 1
-!s100 RT9n9HH7ShGYTRk0Zj<MK3
-InmT0b<BMV7FknI]N:9n7g0
-R1
-R2
-w1590179259
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v
-L0 1
-R3
-r1
-!s85 0
-31
-R9
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v|
-!s101 -O0
-!i113 1
-R5
-n@data@memory
-vInstructionMemory
-Z10 !s110 1590181225
-!i10b 1
-!s100 =6Ye0hT1H9KSDP1=FhXga2
-ISLBgfdW;aN8g[2DAo[I992
-R1
-R2
-w1590180454
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
-L0 1
-R3
-r1
-!s85 0
-31
-Z11 !s108 1590181225.000000
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v|
-!s101 -O0
-!i113 1
-R5
-n@instruction@memory
-vMux32bit
-R6
-!i10b 1
-!s100 6HOE]5bDRSA[<HBJLTnYP0
-InTEk>^`Yjc4Xl2[WnZ3^Y3
-R1
-R2
-Z12 w1589610975
-Z13 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
-Z14 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
-L0 1
-R3
-r1
-!s85 0
-31
-R7
-Z15 !s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
-Z16 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
-!s101 -O0
-!i113 1
-R5
-n@mux32bit
-vMux5bit
-R6
-!i10b 1
-!s100 1oCn>`bHoZ=?A6[JF911T3
-I]EmV`Adl6kHglkN9IK>LX2
-R1
-R2
-R12
-R13
-R14
-L0 16
-R3
-r1
-!s85 0
-31
-R7
-R15
-R16
-!s101 -O0
-!i113 1
-R5
-n@mux5bit
-vRegister
-R10
-!i10b 1
-!s100 Bdb0dL`fj[<g;4lO0DTA?2
-I`9^FTXAAIcP>dnBfah`[e1
-R1
-R2
-w1590176245
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
-L0 1
-R3
-r1
-!s85 0
-31
-R11
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
-!s101 -O0
-!i113 1
-R5
-n@register
-vShiftLeft2
-R10
-!i10b 1
-!s100 eI5Ec:gWMIfN>mTKQIBY93
-IWRY1:Un@<nHGbA7hoKFL[1
-R1
-R2
-w1589586193
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
-L0 1
-R3
-r1
-!s85 0
-31
-R11
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v|
-!s101 -O0
-!i113 1
-R5
-n@shift@left2
-vSignExtend
-R10
-!i10b 1
-!s100 ahVKzC^1fD@70fO3WnVUV0
-Izf_2?i[S@:;mKbJ:CXF753
-R1
-R2
-w1589586199
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
-L0 1
-R3
-r1
-!s85 0
-31
-R11
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v|
-!s101 -O0
-!i113 1
-R5
-n@sign@extend
-vtest
-!s110 1590134078
-!i10b 1
-!s100 Sm5D9nHWJl4JV?TA`lU4`0
-IW:K2A@A@^WBUal;dbVMEN0
-R1
-R2
-w1589610276
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
-L0 1
-R3
-r1
-!s85 0
-31
-!s108 1590134078.000000
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v|
-!s101 -O0
-!i113 1
-R5
-vtestbench
-R10
-!i10b 1
-!s100 5AnCjSMdS0^a=^L0fjCWj2
-IlnGeUJ27C[a2FGBi<YI?;0
-R1
-R2
-w1590179680
-8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
-FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
-L0 1
-R3
-r1
-!s85 0
-31
-R11
-!s107 D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v|
-!s101 -O0
-!i113 1
-R5