module test;

wire clk;
reg sig1;
reg[31:0] in1;
wire[31:0] out1, out2;

Clock clock(clk);
testA ta(clk, sig1, in1, out1, out2);

initial begin
	sig1 <= 1'b0;
	in1 <= 32'd0;
	#100;
	in1 <= 32'hffffffff;
	#100;
	sig1 <= 1'b1;
	in1 <= 32'h0000ffff; 
	#100;
	sig1 <= 1'b1;
	in1 <= 32'hffff0000; 
	#100;
end

/*
wire clk;
reg[31:0] pc;
wire[31:0] instr, tempPC;

Clock clock(clk);
InstructionFetch IF(clk, pc, instr, tempPC);

initial begin
	pc = 32'hfffffffc;
end

always @(negedge clk) begin
	pc = pc + 4;
end
*/
endmodule

module testA(clk, sig1, in1, out1, out2);

input clk, sig1;
input[31:0] in1;
output reg[31:0] out1, out2;

always @(posedge clk) begin
	out1 <= in1;
	if(sig1 == 1) out2 <= in1;
end

endmodule