// Test Required
module MIPS_Pipeline;

wire clk;							// clock
wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		

wire[31:0] instr;						// loaded instruction.

wire[4:0] reg_writereg1;					// register number for the write data.
wire[31:0] reg_writedata;					// data that will be written in the register.
wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.

wire[31:0] alu_input2;						// input data of ALU.
wire[31:0] alu_result;						// result data of ALU.
wire[5:0] alu_branch;						// indicator for branch operation.

wire[31:0] mem_readdata;					// data from the requested address.

wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
wire[3:0] ctrl_aluctrl;						// control signals.
wire[2:0] ctrl_branch;

wire[31:0] extend_output;

wire[31:0] shiftBranch_output;
wire[31:0] shiftJump_output;

// IF_ID register outputs
wire[31:0] ifid_instr, ifid_PC_4;

// ID_EX register outputs
wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg;
wire[3:0] idex_aluctrl; 
wire[2:0] idex_branch;
wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;

// EX_MEM register outputs
wire[4:0] exmem_writereg1;
wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump;
wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;

// MEM_WB register outputs
wire[4:0] memwb_writereg1;
wire memwb_regwrite, memwb_memtoreg, memwb_jump;
wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;


Clock clock(clk);
PCcounter pccounter(clk, nextPC, instr_address);

// Instruction Fetch
InstructionMemory instrmem(instr_address, instr);
Adder add_pc4(PC, 32'h00000004, addPC4);

IF_ID ifid(clk, instr, addPC4, 
	ifid_instr, ifid_PC_4);

// Instruction Decode
Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11],  ctrl_regdst,  reg_writereg1);
Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata,  memwb_regwrite,  reg_readdata1, reg_readdata2);
SignExtend extend(ifid_instr[15:0], extend_output);
ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);

ID_EX idex(clk, reg_writereg1, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 
	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, ifid_instr[25:21], ifid_instr[20:16], 
	idex_writereg1, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 
	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump, idex_readreg_num1, idex_readreg_num2);

// Execute
Mux32bit mux_alusrc(idex_readdata2, idex_extend,  idex_alusrc,  alu_input2);
ALU alu(clk, idex_readdata1, alu_input2,  idex_aluctrl,  alu_result, alu_branch);
ShiftLeft2 shiftBranch(idex_extend, shiftBranch_output);
Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);

EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, 
	alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 
	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, 
	exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);

// Memory
DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exmem_memwrite,  mem_readdata);
Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch,  exmem_branch ,  tempPC_branch);

MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 
	exmem_aluresult, mem_readdata, tempPC_branch, exmem_PCjump, 
	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 
	memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump);

// Writeback
Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  reg_writedata);
Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump,  memwb_jump,  nextPC);




always @(posedge clk) begin

end

/*
wire clk;							// clock
reg[31:0] PC, instr_address;

// IF - ID
wire[31:0] if_id_instruction, if_id_pc_4;

// ID - EX
wire[31:0] id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump;
wire[4:0] id_ex_writereg, id_hh_readreg1, id_hh_readreg2;
wire id_ex_regwrite, id_ex_alusrc, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg;
wire[3:0] id_ex_aluctrl;

// EX - MEM
wire[31:0] ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch;
wire[4:0] ex_mem_writereg;
wire ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump;

// MEM - WB
wire[4:0] mem_wb_writereg_num;
wire mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump;
wire[31:0] mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump;

// WB - etc.
wire wb_id_regwrite;
wire[4:0] wb_id_writereg;
wire[31:0] wb_id_reg_writedata;
wire[31:0] wb_nextPC;

Clock clock(clk);

InstructionFetch IF(clk, PC,  if_id_instruction, if_id_pc_4);

InstructionDecode ID(clk, if_id_instruction, if_id_pc_4, wb_id_writereg, wb_id_reg_writedata, wb_id_regwrite, 
	id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
	id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump);

Execute EX(clk, id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
	id_ex_reg_readdata1,  id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump, 
	ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump, 
	ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch);

Mem MEM(clk, ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump, 
	ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch, 
	mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump);

WriteBack WB(clk, mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump, 
	wb_id_regwrite, wb_id_writereg, wb_id_reg_writedata, wb_nextPC);

initial begin
	PC = 32'hfffffffc;
end

always @(posedge clk) begin
	instr_address = PC;
end

always @(negedge clk) begin
	PC = PC + 4;
end
*/
endmodule