Control.v
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module Control(opcode, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
input[5:0] opcode;
input[5:0] funct;
output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, branch, jump, jumpreg;
output reg[3:0] aluctrl;
always @(*) begin
case(opcode)
6'b000000: begin // R type instruction
regdst = 1'b1;
regwrite = 1'b1;
alusrc = 1'b0;
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
case(funct)
6'b100000: aluctrl = 4'b0010; // add
6'b100001: aluctrl = 4'b0010; // addu
6'b100010: aluctrl = 4'b0110; // sub
6'b100011: aluctrl = 4'b0110; // subu
6'b100100: aluctrl = 4'b0000; // and
6'b100101: aluctrl = 4'b0001; // or
6'b100110: aluctrl = 4'b1101; // xor
6'b011000: aluctrl = 4'b1000; // mult
6'b011001: aluctrl = 4'b1000; // multu
6'b011010: aluctrl = 4'b1001; // div
6'b011011: aluctrl = 4'b1001; // divu
6'b101010: aluctrl = 4'b0111; // slt
6'b101011: aluctrl = 4'b0111; // sltu
6'b010000: aluctrl = 4'b1010; // mfhi
6'b010010: aluctrl = 4'b1011; // mflo
6'b001000: begin // jr
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
jumpreg = 1'b1;
end
default: aluctrl = 4'b1111;
endcase
end
6'b001000: begin // addi instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b001001: begin // addiu instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b001100: begin // andi instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0000; // and
memread = 1'b0;
memwrite = 1'b0;
memtoreg = 1'b0;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000100: begin // beq instruction
// regdst = 1'bx; // don't care
regwrite = 1'b0;
alusrc = 1'b0;
aluctrl = 4'b0110; // sub
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b1;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b000010: begin // jump instruction
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b1;
jumpreg = 1'b0;
end
6'b100011: begin // lw instruction
regdst = 1'b0;
regwrite = 1'b1;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b1;
memwrite = 1'b0;
memtoreg = 1'b1;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
6'b101011: begin // sw instruction
regdst = 1'b0;
regwrite = 1'b0;
alusrc = 1'b1;
aluctrl = 4'b0010; // add
memread = 1'b0;
memwrite = 1'b1;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
default: begin // unknown instruction
// regdst = 1'bx;
regwrite = 1'b0;
// alusrc = 1'bx;
aluctrl = 4'b1111;
memread = 1'b0;
memwrite = 1'b0;
// memtoreg = 1'bx;
branch = 1'b0;
jump = 1'b0;
jumpreg = 1'b0;
end
endcase
end
endmodule