aarch64-bf16-ldst-intrinsics.c
23.5 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
// RUN: -O2 -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK64
// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
// RUN: -O2 -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK32
#include "arm_neon.h"
bfloat16x4_t test_vld1_bf16(bfloat16_t const *ptr) {
return vld1_bf16(ptr);
}
// CHECK-LABEL: test_vld1_bf16
// CHECK64: %1 = load <4 x bfloat>, <4 x bfloat>* %0
// CHECK64-NEXT: ret <4 x bfloat> %1
// CHECK32: %1 = load <4 x bfloat>, <4 x bfloat>* %0, align 2
// CHECK32-NEXT: ret <4 x bfloat> %1
bfloat16x8_t test_vld1q_bf16(bfloat16_t const *ptr) {
return vld1q_bf16(ptr);
}
// CHECK-LABEL: test_vld1q_bf16
// CHECK64: %1 = load <8 x bfloat>, <8 x bfloat>* %0
// CHECK64-NEXT: ret <8 x bfloat> %1
// CHECK32: %1 = load <8 x bfloat>, <8 x bfloat>* %0, align 2
// CHECK32-NEXT: ret <8 x bfloat> %1
bfloat16x4_t test_vld1_lane_bf16(bfloat16_t const *ptr, bfloat16x4_t src) {
return vld1_lane_bf16(ptr, src, 0);
}
// CHECK-LABEL: test_vld1_lane_bf16
// CHECK64: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK64-NEXT: %vld1_lane = insertelement <4 x bfloat> %src, bfloat %0, i32 0
// CHECK64-NEXT: ret <4 x bfloat> %vld1_lane
// CHECK32: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK32-NEXT: %vld1_lane = insertelement <4 x bfloat> %src, bfloat %0, i32 0
// CHECK32-NEXT: ret <4 x bfloat> %vld1_lane
bfloat16x8_t test_vld1q_lane_bf16(bfloat16_t const *ptr, bfloat16x8_t src) {
return vld1q_lane_bf16(ptr, src, 7);
}
// CHECK-LABEL: test_vld1q_lane_bf16
// CHECK64: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK64-NEXT: %vld1_lane = insertelement <8 x bfloat> %src, bfloat %0, i32 7
// CHECK64-NEXT: ret <8 x bfloat> %vld1_lane
// CHECK32: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK32-NEXT: %vld1_lane = insertelement <8 x bfloat> %src, bfloat %0, i32 7
// CHECK32-NEXT: ret <8 x bfloat> %vld1_lane
bfloat16x4_t test_vld1_dup_bf16(bfloat16_t const *ptr) {
return vld1_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld1_dup_bf16
// CHECK64: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK64-NEXT: %1 = insertelement <4 x bfloat> undef, bfloat %0, i32 0
// CHECK64-NEXT: %lane = shufflevector <4 x bfloat> %1, <4 x bfloat> undef, <4 x i32> zeroinitializer
// CHECK64-NEXT: ret <4 x bfloat> %lane
// CHECK32: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK32-NEXT: %1 = insertelement <4 x bfloat> undef, bfloat %0, i32 0
// CHECK32-NEXT: %lane = shufflevector <4 x bfloat> %1, <4 x bfloat> undef, <4 x i32> zeroinitializer
// CHECK32-NEXT: ret <4 x bfloat> %lane
bfloat16x4x2_t test_vld1_bf16_x2(bfloat16_t const *ptr) {
return vld1_bf16_x2(ptr);
}
// CHECK-LABEL: test_vld1_bf16_x2
// CHECK64: %vld1xN = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x2.v4bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld1xN = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x2.v4bf16.p0bf16(bfloat* %ptr)
bfloat16x8x2_t test_vld1q_bf16_x2(bfloat16_t const *ptr) {
return vld1q_bf16_x2(ptr);
}
// CHECK-LABEL: test_vld1q_bf16_x2
// CHECK64: %vld1xN = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x2.v8bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld1xN = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x2.v8bf16.p0bf16(bfloat* %ptr)
bfloat16x4x3_t test_vld1_bf16_x3(bfloat16_t const *ptr) {
return vld1_bf16_x3(ptr);
}
// CHECK-LABEL: test_vld1_bf16_x3
// CHECK64: %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x3.v4bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x3.v4bf16.p0bf16(bfloat* %ptr)
bfloat16x8x3_t test_vld1q_bf16_x3(bfloat16_t const *ptr) {
return vld1q_bf16_x3(ptr);
}
// CHECK-LABEL: test_vld1q_bf16_x3
// CHECK64: %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x3.v8bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x3.v8bf16.p0bf16(bfloat* %ptr)
bfloat16x4x4_t test_vld1_bf16_x4(bfloat16_t const *ptr) {
return vld1_bf16_x4(ptr);
}
// CHECK-LABEL: test_vld1_bf16_x4
// CHECK64: %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x4.v4bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x4.v4bf16.p0bf16(bfloat* %ptr)
bfloat16x8x4_t test_vld1q_bf16_x4(bfloat16_t const *ptr) {
return vld1q_bf16_x4(ptr);
}
// CHECK-LABEL: test_vld1q_bf16_x4
// CHECK64: %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld1x4.v8bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld1xN = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld1x4.v8bf16.p0bf16(bfloat* %ptr)
bfloat16x8_t test_vld1q_dup_bf16(bfloat16_t const *ptr) {
return vld1q_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld1q_dup_bf16
// CHECK64: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK64-NEXT: %1 = insertelement <8 x bfloat> undef, bfloat %0, i32 0
// CHECK64-NEXT: %lane = shufflevector <8 x bfloat> %1, <8 x bfloat> undef, <8 x i32> zeroinitializer
// CHECK64-NEXT: ret <8 x bfloat> %lane
// CHECK32: %0 = load bfloat, bfloat* %ptr, align 2
// CHECK32-NEXT: %1 = insertelement <8 x bfloat> undef, bfloat %0, i32 0
// CHECK32-NEXT: %lane = shufflevector <8 x bfloat> %1, <8 x bfloat> undef, <8 x i32> zeroinitializer
// CHECK32-NEXT: ret <8 x bfloat> %lane
bfloat16x4x2_t test_vld2_bf16(bfloat16_t const *ptr) {
return vld2_bf16(ptr);
}
// CHECK-LABEL: test_vld2_bf16
// CHECK64: %0 = bitcast bfloat* %ptr to <4 x bfloat>*
// CHECK64-NEXT: %vld2 = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2.v4bf16.p0v4bf16(<4 x bfloat>* %0)
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld2_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2.v4bf16.p0i8(i8* %0, i32 2)
bfloat16x8x2_t test_vld2q_bf16(bfloat16_t const *ptr) {
return vld2q_bf16(ptr);
}
// CHECK-LABEL: test_vld2q_bf16
// CHECK64: %0 = bitcast bfloat* %ptr to <8 x bfloat>*
// CHECK64-NEXT: %vld2 = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2.v8bf16.p0v8bf16(<8 x bfloat>* %0)
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld2q_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2.v8bf16.p0i8(i8* %0, i32 2)
bfloat16x4x2_t test_vld2_lane_bf16(bfloat16_t const *ptr, bfloat16x4x2_t src) {
return vld2_lane_bf16(ptr, src, 1);
}
// CHECK-LABEL: test_vld2_lane_bf16
// CHECK64: %vld2_lane = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2lane.v4bf16.p0i8(<4 x bfloat> %src.coerce.fca.0.extract, <4 x bfloat> %src.coerce.fca.1.extract, i64 1, i8* %0)
// CHECK32: %vld2_lane_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2lane.v4bf16.p0i8(i8* %2, <4 x bfloat> %0, <4 x bfloat> %1, i32 1, i32 2)
bfloat16x8x2_t test_vld2q_lane_bf16(bfloat16_t const *ptr, bfloat16x8x2_t src) {
return vld2q_lane_bf16(ptr, src, 7);
}
// CHECK-LABEL: test_vld2q_lane_bf16
// CHECK64: %vld2_lane = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2lane.v8bf16.p0i8(<8 x bfloat> %src.coerce.fca.0.extract, <8 x bfloat> %src.coerce.fca.1.extract, i64 7, i8* %0)
// CHECK32: %vld2q_lane_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2lane.v8bf16.p0i8(i8* %2, <8 x bfloat> %0, <8 x bfloat> %1, i32 7, i32 2)
bfloat16x4x3_t test_vld3_bf16(bfloat16_t const *ptr) {
return vld3_bf16(ptr);
}
// CHECK-LABEL: test_vld3_bf16
// CHECK64: %vld3 = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld3.v4bf16.p0v4bf16(<4 x bfloat>* %0)
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld3_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3.v4bf16.p0i8(i8* %0, i32 2)
bfloat16x8x3_t test_vld3q_bf16(bfloat16_t const *ptr) {
return vld3q_bf16(ptr);
}
// CHECK-LABEL: test_vld3q_bf16
// CHECK64: %vld3 = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld3.v8bf16.p0v8bf16(<8 x bfloat>* %0)
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld3q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3.v8bf16.p0i8(i8* %0, i32 2)
bfloat16x4x3_t test_vld3_lane_bf16(bfloat16_t const *ptr, bfloat16x4x3_t src) {
return vld3_lane_bf16(ptr, src, 1);
}
// CHECK-LABEL: test_vld3_lane_bf16
// CHECK64: %vld3_lane = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld3lane.v4bf16.p0i8(<4 x bfloat> %src.coerce.fca.0.extract, <4 x bfloat> %src.coerce.fca.1.extract, <4 x bfloat> %src.coerce.fca.2.extract, i64 1, i8* %0)
// CHECK32: %3 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld3_lane_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3lane.v4bf16.p0i8(i8* %3, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 1, i32 2)
bfloat16x8x3_t test_vld3q_lane_bf16(bfloat16_t const *ptr, bfloat16x8x3_t src) {
return vld3q_lane_bf16(ptr, src, 7);
// return vld3q_lane_bf16(ptr, src, 8);
}
// CHECK-LABEL: test_vld3q_lane_bf16
// CHECK64: %vld3_lane = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld3lane.v8bf16.p0i8(<8 x bfloat> %src.coerce.fca.0.extract, <8 x bfloat> %src.coerce.fca.1.extract, <8 x bfloat> %src.coerce.fca.2.extract, i64 7, i8* %0)
// CHECK32: %3 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld3q_lane_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3lane.v8bf16.p0i8(i8* %3, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 7, i32 2)
bfloat16x4x4_t test_vld4_bf16(bfloat16_t const *ptr) {
return vld4_bf16(ptr);
}
// CHECK-LABEL: test_vld4_bf16
// CHECK64: %vld4 = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld4.v4bf16.p0v4bf16(<4 x bfloat>* %0)
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld4_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4.v4bf16.p0i8(i8* %0, i32 2)
bfloat16x8x4_t test_vld4q_bf16(bfloat16_t const *ptr) {
return vld4q_bf16(ptr);
}
// CHECK-LABEL: test_vld4q_bf16
// CHECK64: %vld4 = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld4.v8bf16.p0v8bf16(<8 x bfloat>* %0)
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld4q_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4.v8bf16.p0i8(i8* %0, i32 2)
bfloat16x4x4_t test_vld4_lane_bf16(bfloat16_t const *ptr, bfloat16x4x4_t src) {
return vld4_lane_bf16(ptr, src, 1);
}
// CHECK-LABEL: test_vld4_lane_bf16
// CHECK64: %vld4_lane = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld4lane.v4bf16.p0i8(<4 x bfloat> %src.coerce.fca.0.extract, <4 x bfloat> %src.coerce.fca.1.extract, <4 x bfloat> %src.coerce.fca.2.extract, <4 x bfloat> %src.coerce.fca.3.extract, i64 1, i8* %0)
// CHECK32: %4 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld4_lane_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4lane.v4bf16.p0i8(i8* %4, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 1, i32 2)
bfloat16x8x4_t test_vld4q_lane_bf16(bfloat16_t const *ptr, bfloat16x8x4_t src) {
return vld4q_lane_bf16(ptr, src, 7);
}
// CHECK-LABEL: test_vld4q_lane_bf16
// CHECK64: %vld4_lane = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld4lane.v8bf16.p0i8(<8 x bfloat> %src.coerce.fca.0.extract, <8 x bfloat> %src.coerce.fca.1.extract, <8 x bfloat> %src.coerce.fca.2.extract, <8 x bfloat> %src.coerce.fca.3.extract, i64 7, i8* %0)
// CHECK32: %4 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: %vld4q_lane_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4lane.v8bf16.p0i8(i8* %4, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 7, i32 2)
bfloat16x4x2_t test_vld2_dup_bf16(bfloat16_t const *ptr) {
return vld2_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld2_dup_bf16
// CHECK64: %vld2 = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2r.v4bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld2_dup_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2dup.v4bf16.p0i8(i8* %0, i32 2)
bfloat16x8x2_t test_vld2q_dup_bf16(bfloat16_t const *ptr) {
return vld2q_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld2q_dup_bf16
// CHECK64: %vld2 = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld2r.v8bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld2q_dup_v = tail call { <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld2dup.v8bf16.p0i8(i8* %0, i32 2)
bfloat16x4x3_t test_vld3_dup_bf16(bfloat16_t const *ptr) {
return vld3_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld3_dup_bf16
// CHECK64: %vld3 = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld3r.v4bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld3_dup_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3dup.v4bf16.p0i8(i8* %0, i32 2)
bfloat16x8x3_t test_vld3q_dup_bf16(bfloat16_t const *ptr) {
return vld3q_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld3q_dup_bf16
// CHECK64: %vld3 = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld3r.v8bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld3q_dup_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld3dup.v8bf16.p0i8(i8* %0, i32 2)
bfloat16x4x4_t test_vld4_dup_bf16(bfloat16_t const *ptr) {
return vld4_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld4_dup_bf16
// CHECK64: %vld4 = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld4r.v4bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld4_dup_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4dup.v4bf16.p0i8(i8* %0, i32 2)
bfloat16x8x4_t test_vld4q_dup_bf16(bfloat16_t const *ptr) {
return vld4q_dup_bf16(ptr);
}
// CHECK-LABEL: test_vld4q_dup_bf16
// CHECK64: %vld4 = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.aarch64.neon.ld4r.v8bf16.p0bf16(bfloat* %ptr)
// CHECK32: %vld4q_dup_v = tail call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.arm.neon.vld4dup.v8bf16.p0i8(i8* %0, i32 2)
void test_vst1_bf16(bfloat16_t *ptr, bfloat16x4_t val) {
vst1_bf16(ptr, val);
}
// CHECK-LABEL: test_vst1_bf16
// CHECK64: %0 = bitcast bfloat* %ptr to <4 x bfloat>*
// CHECK64-NEXT: store <4 x bfloat> %val, <4 x bfloat>* %0, align 2
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: tail call void @llvm.arm.neon.vst1.p0i8.v4bf16(i8* %0, <4 x bfloat> %val, i32 2)
void test_vst1q_bf16(bfloat16_t *ptr, bfloat16x8_t val) {
vst1q_bf16(ptr, val);
}
// CHECK-LABEL: test_vst1q_bf16
// CHECK64: %0 = bitcast bfloat* %ptr to <8 x bfloat>*
// CHECK64-NEXT: store <8 x bfloat> %val, <8 x bfloat>* %0, align 2
// CHECK32: %0 = bitcast bfloat* %ptr to i8*
// CHECK32-NEXT: tail call void @llvm.arm.neon.vst1.p0i8.v8bf16(i8* %0, <8 x bfloat> %val, i32 2)
void test_vst1_lane_bf16(bfloat16_t *ptr, bfloat16x4_t val) {
vst1_lane_bf16(ptr, val, 1);
}
// CHECK-LABEL: test_vst1_lane_bf16
// CHECK64: %0 = extractelement <4 x bfloat> %val, i32 1
// CHECK64-NEXT: store bfloat %0, bfloat* %ptr, align 2
// CHECK32: %0 = extractelement <4 x bfloat> %val, i32 1
// CHECK32-NEXT: store bfloat %0, bfloat* %ptr, align 2
void test_vst1q_lane_bf16(bfloat16_t *ptr, bfloat16x8_t val) {
vst1q_lane_bf16(ptr, val, 7);
}
// CHECK-LABEL: test_vst1q_lane_bf16
// CHECK64: %0 = extractelement <8 x bfloat> %val, i32 7
// CHECK64-NEXT: store bfloat %0, bfloat* %ptr, align 2
// CHECK32: %0 = extractelement <8 x bfloat> %val, i32 7
// CHECK32-NEXT: store bfloat %0, bfloat* %ptr, align 2
void test_vst1_bf16_x2(bfloat16_t *ptr, bfloat16x4x2_t val) {
vst1_bf16_x2(ptr, val);
}
// CHECK-LABEL: test_vst1_bf16_x2
// CHECK64: tail call void @llvm.aarch64.neon.st1x2.v4bf16.p0bf16(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, bfloat* %ptr)
// CHECK32: tail call void @llvm.arm.neon.vst1x2.p0bf16.v4bf16(bfloat* %ptr, <4 x bfloat> %0, <4 x bfloat> %1)
void test_vst1q_bf16_x2(bfloat16_t *ptr, bfloat16x8x2_t val) {
vst1q_bf16_x2(ptr, val);
}
// CHECK-LABEL: test_vst1q_bf16_x2
// CHECK64: tail call void @llvm.aarch64.neon.st1x2.v8bf16.p0bf16(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, bfloat* %ptr)
// CHECK32: tail call void @llvm.arm.neon.vst1x2.p0bf16.v8bf16(bfloat* %ptr, <8 x bfloat> %0, <8 x bfloat> %1)
void test_vst1_bf16_x3(bfloat16_t *ptr, bfloat16x4x3_t val) {
vst1_bf16_x3(ptr, val);
}
// CHECK-LABEL: test_vst1_bf16_x3
// CHECK64: tail call void @llvm.aarch64.neon.st1x3.v4bf16.p0bf16(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extract, bfloat* %ptr)
// CHECK32: tail call void @llvm.arm.neon.vst1x3.p0bf16.v4bf16(bfloat* %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2)
void test_vst1q_bf16_x3(bfloat16_t *ptr, bfloat16x8x3_t val) {
vst1q_bf16_x3(ptr, val);
}
// CHECK-LABEL: test_vst1q_bf16_x3
// CHECK64: tail call void @llvm.aarch64.neon.st1x3.v8bf16.p0bf16(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extract, bfloat* %ptr)
// CHECK32: tail call void @llvm.arm.neon.vst1x3.p0bf16.v8bf16(bfloat* %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2)
void test_vst1_bf16_x4(bfloat16_t *ptr, bfloat16x4x4_t val) {
vst1_bf16_x4(ptr, val);
}
// CHECK-LABEL: test_vst1_bf16_x4
// CHECK64: tail call void @llvm.aarch64.neon.st1x4.v4bf16.p0bf16(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extract, <4 x bfloat> %val.coerce.fca.3.extract, bfloat* %ptr)
// CHECK32: tail call void @llvm.arm.neon.vst1x4.p0bf16.v4bf16(bfloat* %ptr, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3)
void test_vst1q_bf16_x4(bfloat16_t *ptr, bfloat16x8x4_t val) {
vst1q_bf16_x4(ptr, val);
}
// CHECK-LABEL: test_vst1q_bf16_x4
// CHECK64: tail call void @llvm.aarch64.neon.st1x4.v8bf16.p0bf16(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extract, <8 x bfloat> %val.coerce.fca.3.extract, bfloat* %ptr)
// CHECK32: tail call void @llvm.arm.neon.vst1x4.p0bf16.v8bf16(bfloat* %ptr, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3)
void test_vst2_bf16(bfloat16_t *ptr, bfloat16x4x2_t val) {
vst2_bf16(ptr, val);
}
// CHECK-LABEL: test_vst2_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st2.v4bf16.p0i8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst2.p0i8.v4bf16(i8* %2, <4 x bfloat> %0, <4 x bfloat> %1, i32 2)
void test_vst2q_bf16(bfloat16_t *ptr, bfloat16x8x2_t val) {
vst2q_bf16(ptr, val);
}
// CHECK-LABEL: test_vst2q_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st2.v8bf16.p0i8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst2.p0i8.v8bf16(i8* %2, <8 x bfloat> %0, <8 x bfloat> %1, i32 2)
void test_vst2_lane_bf16(bfloat16_t *ptr, bfloat16x4x2_t val) {
vst2_lane_bf16(ptr, val, 1);
}
// CHECK-LABEL: test_vst2_lane_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st2lane.v4bf16.p0i8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, i64 1, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst2lane.p0i8.v4bf16(i8* %2, <4 x bfloat> %0, <4 x bfloat> %1, i32 1, i32 2)
void test_vst2q_lane_bf16(bfloat16_t *ptr, bfloat16x8x2_t val) {
vst2q_lane_bf16(ptr, val, 7);
}
// CHECK-LABEL: test_vst2q_lane_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st2lane.v8bf16.p0i8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, i64 7, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst2lane.p0i8.v8bf16(i8* %2, <8 x bfloat> %0, <8 x bfloat> %1, i32 7, i32 2)
void test_vst3_bf16(bfloat16_t *ptr, bfloat16x4x3_t val) {
vst3_bf16(ptr, val);
}
// CHECK-LABEL: test_vst3_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st3.v4bf16.p0i8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extract, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst3.p0i8.v4bf16(i8* %3, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 2)
void test_vst3q_bf16(bfloat16_t *ptr, bfloat16x8x3_t val) {
vst3q_bf16(ptr, val);
}
// CHECK-LABEL: test_vst3q_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st3.v8bf16.p0i8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extract, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst3.p0i8.v8bf16(i8* %3, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 2)
void test_vst3_lane_bf16(bfloat16_t *ptr, bfloat16x4x3_t val) {
vst3_lane_bf16(ptr, val, 1);
}
// CHECK-LABEL: test_vst3_lane_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st3lane.v4bf16.p0i8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extract, i64 1, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst3lane.p0i8.v4bf16(i8* %3, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, i32 1, i32 2)
void test_vst3q_lane_bf16(bfloat16_t *ptr, bfloat16x8x3_t val) {
vst3q_lane_bf16(ptr, val, 7);
}
// CHECK-LABEL: test_vst3q_lane_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st3lane.v8bf16.p0i8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extract, i64 7, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst3lane.p0i8.v8bf16(i8* %3, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, i32 7, i32 2)
void test_vst4_bf16(bfloat16_t *ptr, bfloat16x4x4_t val) {
vst4_bf16(ptr, val);
}
// CHECK-LABEL: test_vst4_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st4.v4bf16.p0i8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extract, <4 x bfloat> %val.coerce.fca.3.extract, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst4.p0i8.v4bf16(i8* %4, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 2)
void test_vst4q_bf16(bfloat16_t *ptr, bfloat16x8x4_t val) {
vst4q_bf16(ptr, val);
}
// CHECK-LABEL: test_vst4q_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st4.v8bf16.p0i8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extract, <8 x bfloat> %val.coerce.fca.3.extract, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst4.p0i8.v8bf16(i8* %4, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 2)
void test_vst4_lane_bf16(bfloat16_t *ptr, bfloat16x4x4_t val) {
vst4_lane_bf16(ptr, val, 1);
}
// CHECK-LABEL: test_vst4_lane_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st4lane.v4bf16.p0i8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extract, <4 x bfloat> %val.coerce.fca.3.extract, i64 1, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst4lane.p0i8.v4bf16(i8* %4, <4 x bfloat> %0, <4 x bfloat> %1, <4 x bfloat> %2, <4 x bfloat> %3, i32 1, i32 2)
void test_vst4q_lane_bf16(bfloat16_t *ptr, bfloat16x8x4_t val) {
vst4q_lane_bf16(ptr, val, 7);
}
// CHECK-LABEL: test_vst4q_lane_bf16
// CHECK64: tail call void @llvm.aarch64.neon.st4lane.v8bf16.p0i8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extract, <8 x bfloat> %val.coerce.fca.3.extract, i64 7, i8* %0)
// CHECK32: tail call void @llvm.arm.neon.vst4lane.p0i8.v8bf16(i8* %4, <8 x bfloat> %0, <8 x bfloat> %1, <8 x bfloat> %2, <8 x bfloat> %3, i32 7, i32 2)