mve-ctlz.ll
4.03 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov s6, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: vldr s5, .LCPI0_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0x00000000 @ float 0
entry:
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0)
ret <2 x i64> %0
}
define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){
; CHECK-LABEL: ctlz_4i32_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i32 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 0)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_0_t(<8 x i16> %src){
; CHECK-LABEL: ctlz_8i16_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 0)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_0_t(<16 x i8> %src){
; CHECK-LABEL: ctlz_16i8_0_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i8 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 0)
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov s6, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: add.w r1, r1, #32
; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: vldr s5, .LCPI4_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI4_0:
; CHECK-NEXT: .long 0x00000000 @ float 0
entry:
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1)
ret <2 x i64> %0
}
define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){
; CHECK-LABEL: ctlz_4i32_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i32 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 1)
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_1_t(<8 x i16> %src){
; CHECK-LABEL: ctlz_8i16_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 1)
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_1_t(<16 x i8> %src){
; CHECK-LABEL: ctlz_16i8_1_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vclz.i8 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 1)
ret <16 x i8> %0
}
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)