regcoal-subranges-update.mir
3.61 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple s390x-ibm-linux -mcpu=z13 -systemz-subreg-liveness -verify-machineinstrs -start-before simple-register-coalescing -stop-after greedy -o - %s | FileCheck %s
# Check that when we split the live-range with several active lanes
# as part of the live-range update, we correctly eliminate the VNI from
# the relevant part.
#
# In this specific test, the register coalescer will:
# 1. Merge %0 with %1, creating a live-range for the full value subreg_l32 + subreg_h32
# (actually %0 gets merge with %1 via rematerialization, and technically %0 and %1
# remain two different live-ranges.)
# 2. Merge %2 with %1 triggering a split into the subreg_l32 + subreg_h32 ranges, since
# %2 only touches subreg_l32. As part of the split the subrange covering subreg_h32
# must contain only the VNI for the high part (i.e., the one tied with the remaaat of %0).
# This used to be broken and trigger a machine verifier error, because we were not
# clearing the dead value w.r.t. lanes when doing the splitting. I.e., we were ending
# with a subrange referring a value that did not define that lane.
#
# PR40835
---
name: main
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: main
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43
; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
; CHECK: [[LGHI1]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
; CHECK: [[LGHI1]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
; CHECK: undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
; CHECK: [[DLGR:%[0-9]+]]:gr128bit = DLGR [[DLGR]], [[LGHI]]
; CHECK: Return implicit [[DLGR]]
%0:gr64bit = LGHI 43
%1:gr32bit = COPY %0.subreg_l32
%1:gr32bit = MSR %1, %1
%2:gr32bit = COPY killed %1
%2:gr32bit = AHIMux killed %2, 9, implicit-def dead $cc
undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit killed %2
%3:gr128bit = DLGR %3:gr128bit, killed %0
Return implicit killed %3
...
# Make sure the compiler does not choke on VNIs that don't
# an explicit MI as definition.
# In that specific example, this is the PHI not explicitly
# represented for the value carried by %7.
---
name: segfault
tracksRegLiveness: true
liveins: []
body: |
; CHECK-LABEL: name: segfault
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0
; CHECK: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
; CHECK: $r2d = LGHI 123
; CHECK: $r3d = LGHI 0
; CHECK: $r4d = LGHI 0
; CHECK: $r5d = COPY [[LGFR]]
; CHECK: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
; CHECK: ADJCALLSTACKUP 0, 0
; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
; CHECK: J %bb.1
bb.0:
successors: %bb.1(0x80000000)
%2:gr64bit = LGHI 0
%5:gr64bit = LGHI 123
%7:addr64bit = COPY %2
bb.1:
successors: %bb.1(0x80000000)
%0:addr64bit = COPY killed %7
ADJCALLSTACKDOWN 0, 0
%3:gr32bit = COPY %0.subreg_l32
%4:gr64bit = LGFR killed %3
$r2d = COPY %5
$r3d = COPY %2
$r4d = COPY %2
$r5d = COPY killed %4
KILL killed $r2d, killed $r3d, killed $r4d, killed $r5d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
ADJCALLSTACKUP 0, 0
%1:gr64bit = nuw nsw LA killed %0, 1, $noreg
%7:addr64bit = COPY killed %1
J %bb.1
...