botheightreduce.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=machine-scheduler -o - %s | FileCheck %s
---
# Check that machine-scheduler's BotHeightReduce heuristic puts the LD 8 in
# between the final run of MULLDs and the LDXs that feed them, to try to hide
# the latency of the LDXs.
name: test
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $x3, $x4
; CHECK: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x4
; CHECK: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
; CHECK: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY1]], 1
; CHECK: [[CMPLDI:%[0-9]+]]:crrc = CMPLDI [[COPY]], 1
; CHECK: [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
; CHECK: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[COPY]], [[LI8_]], [[CMPLDI]].sub_gt
; CHECK: MTCTR8loop [[ISEL8_]], implicit-def dead $ctr8
; CHECK: [[LI8_1:%[0-9]+]]:g8rc = LI8 0
; CHECK: [[LI8_2:%[0-9]+]]:g8rc = LI8 2
; CHECK: [[LI8_3:%[0-9]+]]:g8rc = LI8 3
; CHECK: [[LI8_4:%[0-9]+]]:g8rc = LI8 5
; CHECK: [[LI8_5:%[0-9]+]]:g8rc = LI8 6
; CHECK: [[LI8_6:%[0-9]+]]:g8rc = LI8 7
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 [[ADDI8_]], 1
; CHECK: [[LD:%[0-9]+]]:g8rc = LD 0, [[ADDI8_]] :: (load 8)
; CHECK: [[LDX:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_]] :: (load 8)
; CHECK: [[LDX1:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_3]] :: (load 8)
; CHECK: [[LD1:%[0-9]+]]:g8rc = LD 4, [[ADDI8_]] :: (load 8)
; CHECK: [[LDX2:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_4]] :: (load 8)
; CHECK: [[LDX3:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_5]] :: (load 8)
; CHECK: [[LDX4:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_6]] :: (load 8)
; CHECK: [[LDX5:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_2]] :: (load 8)
; CHECK: [[MULLD:%[0-9]+]]:g8rc = MULLD [[LDX]], [[LD]]
; CHECK: [[LD2:%[0-9]+]]:g8rc = LD 8, [[ADDI8_]] :: (load 8)
; CHECK: [[MULLD1:%[0-9]+]]:g8rc = MULLD [[MULLD]], [[LDX5]]
; CHECK: [[MULLD2:%[0-9]+]]:g8rc = MULLD [[MULLD1]], [[LDX1]]
; CHECK: [[MULLD3:%[0-9]+]]:g8rc = MULLD [[MULLD2]], [[LD1]]
; CHECK: [[MULLD4:%[0-9]+]]:g8rc = MULLD [[MULLD3]], [[LDX2]]
; CHECK: [[MULLD5:%[0-9]+]]:g8rc = MULLD [[MULLD4]], [[LDX3]]
; CHECK: [[MULLD6:%[0-9]+]]:g8rc = MULLD [[MULLD5]], [[LDX4]]
; CHECK: [[MADDLD8_:%[0-9]+]]:g8rc = MADDLD8 [[MULLD6]], [[LD2]], [[MADDLD8_]]
; CHECK: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_1]]
; CHECK: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
; CHECK: B %bb.2
; CHECK: bb.2:
bb.0:
liveins: $x3, $x4
%0:g8rc_and_g8rc_nox0 = COPY $x4
%1:g8rc_and_g8rc_nox0 = COPY $x3
%2:g8rc_and_g8rc_nox0 = ADDI8 %1, 1
%3:crrc = CMPLDI %0, 1
%4:g8rc_and_g8rc_nox0 = LI8 1
%5:g8rc = ISEL8 %0, %4, %3.sub_gt
MTCTR8loop %5, implicit-def dead $ctr8
%6:g8rc = LI8 0
%7:g8rc = LI8 2
%8:g8rc = LI8 3
%9:g8rc = LI8 5
%10:g8rc = LI8 6
%11:g8rc = LI8 7
bb.1:
%12:g8rc = ADDI8 %2, 1
%13:g8rc = LD 0, %2 :: (load 8)
%14:g8rc = LDX %2, %4 :: (load 8)
%16:g8rc = LDX %2, %8 :: (load 8)
%17:g8rc = LD 4, %2 :: (load 8)
%18:g8rc = LDX %2, %9 :: (load 8)
%19:g8rc = LDX %2, %10 :: (load 8)
%20:g8rc = LDX %2, %11 :: (load 8)
%21:g8rc = LD 8, %2 :: (load 8)
%22:g8rc = MULLD %14, %13
%15:g8rc = LDX %2, %7 :: (load 8)
%23:g8rc = MULLD %22, %15
%24:g8rc = MULLD %23, %16
%25:g8rc = MULLD %24, %17
%26:g8rc = MULLD %25, %18
%27:g8rc = MULLD %26, %19
%28:g8rc = MULLD %27, %20
%6:g8rc = MADDLD8 %28, %21, %6
%2:g8rc_and_g8rc_nox0 = COPY %12
BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8
B %bb.2
bb.2:
...