float-helpers.s 37.5 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -asm-verbose=false -mattr=-vfp2 -mtriple=arm-eabi < %s | FileCheck %s -check-prefix=CHECK-SOFT
; RUN: llc -asm-verbose=false -mattr=-vfp2 -mtriple=arm-eabi -meabi=gnu < %s | FileCheck %s -check-prefix=CHECK-SOFT
; RUN: llc -asm-verbose=false -mattr=+vfp3 -mtriple=arm-eabi < %s | FileCheck %s -check-prefix=CHECK-SOFTFP
; RUN: llc -asm-verbose=false -mattr=+vfp3 -meabi=gnu -mtriple=arm-eabi < %s | FileCheck %s -check-prefix=CHECK-SOFTFP
; RUN: llc -asm-verbose=false -mattr=+vfp3 -float-abi=hard -mtriple=arm-eabi < %s | FileCheck %s -check-prefix=CHECK-HARDFP-SP -check-prefix=CHECK-HARDFP-DP
; RUN: llc -asm-verbose=false -mattr=+vfp3 -float-abi=hard -meabi=gnu -mtriple=arm-eabi < %s | FileCheck %s -check-prefix=CHECK-HARDFP-SP -check-prefix=CHECK-HARDFP-DP
; RUN: llc -asm-verbose=false -mattr=+vfp3,-fp64 -float-abi=hard -mtriple=arm-eabi < %s | FileCheck %s -check-prefix=CHECK-HARDFP-SP -check-prefix=CHECK-HARDFP-SPONLY
; RUN: llc -asm-verbose=false -mattr=+vfp3,-fp64 -float-abi=hard -mtriple=arm-eabi -meabi=gnu < %s | FileCheck %s -check-prefix=CHECK-HARDFP-SP -check-prefix=CHECK-HARDFP-SPONLY

; The Runtime ABI for the ARM Architecture IHI0043 section 4.1.2 The
; floating-point helper functions to always use the base AAPCS (soft-float)
; calling convention.

; In this test we cover the following configurations:
; CHECK-SOFT -mfloat-abi=soft
;     * expect no use of floating point instructions
;     * expect to use __aeabi_ helper function in each function
; CHECK-SOFTFP -mfloat-abi=softfp
;     * all functions use base AAPCS
;     * floating point instructions permitted, so __aeabi_ helpers only
;       expected when there is no available instruction.
; CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions)
;     * all non Runtime ABI helper functions use AAPCS VFP
;     * floating point instructions permitted, so __aeabi_ helpers only
;       expected when there is no available instruction.
; CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions)
; CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single
;                      precision only FPU)
;     * as CHECK-HARDFP-SP, but we split up the double precision helper
;       functions so we can test a single precision only FPU, which has to use
;       helper function for all double precision operations.

; In all cases we must use base AAPCS when calling a helper function from
; section 4.1.2.

target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "arm-eabi"

define float @fadd(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fadd:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fadd
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fadd:
; CHECK-SOFTFP:         vmov s0, r1
; CHECK-SOFTFP-NEXT:    vmov s2, r0
; CHECK-SOFTFP-NEXT:    vadd.f32 s0, s2, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fadd:
; CHECK-HARDFP-SP:         vadd.f32 s0, s0, s1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %add = fadd float %a, %b
  ret float %add
}

define float @fdiv(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fdiv:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fdiv
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fdiv:
; CHECK-SOFTFP:         vmov s0, r1
; CHECK-SOFTFP-NEXT:    vmov s2, r0
; CHECK-SOFTFP-NEXT:    vdiv.f32 s0, s2, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fdiv:
; CHECK-HARDFP-SP:         vdiv.f32 s0, s0, s1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %div = fdiv float %a, %b
  ret float %div
}

define float @fmul(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fmul:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fmul
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fmul:
; CHECK-SOFTFP:         vmov s0, r1
; CHECK-SOFTFP-NEXT:    vmov s2, r0
; CHECK-SOFTFP-NEXT:    vmul.f32 s0, s2, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fmul:
; CHECK-HARDFP-SP:         vmul.f32 s0, s0, s1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %mul = fmul float %a, %b
  ret float %mul
}

define float @fsub(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fsub:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fsub
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fsub:
; CHECK-SOFTFP:         vmov s0, r1
; CHECK-SOFTFP-NEXT:    vmov s2, r0
; CHECK-SOFTFP-NEXT:    vsub.f32 s0, s2, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fsub:
; CHECK-HARDFP-SP:         vsub.f32 s0, s0, s1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %sub = fsub float %a, %b
  ret float %sub
}

define i32 @fcmpeq(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fcmpeq:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fcmpeq
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fcmpeq:
; CHECK-SOFTFP:         vmov s2, r0
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vmov s0, r1
; CHECK-SOFTFP-NEXT:    vcmp.f32 s2, s0
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    moveq r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fcmpeq:
; CHECK-HARDFP-SP:         vcmp.f32 s0, s1
; CHECK-HARDFP-SP-NEXT:    mov r0, #0
; CHECK-HARDFP-SP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-SP-NEXT:    moveq r0, #1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %cmp = fcmp oeq float %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @fcmplt(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fcmplt:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fcmplt
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fcmplt:
; CHECK-SOFTFP:         vmov s2, r0
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vmov s0, r1
; CHECK-SOFTFP-NEXT:    vcmp.f32 s2, s0
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movmi r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fcmplt:
; CHECK-HARDFP-SP:         vcmp.f32 s0, s1
; CHECK-HARDFP-SP-NEXT:    mov r0, #0
; CHECK-HARDFP-SP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-SP-NEXT:    movmi r0, #1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %cmp = fcmp olt float %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @fcmple(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fcmple:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fcmple
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fcmple:
; CHECK-SOFTFP:         vmov s2, r0
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vmov s0, r1
; CHECK-SOFTFP-NEXT:    vcmp.f32 s2, s0
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movls r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fcmple:
; CHECK-HARDFP-SP:         vcmp.f32 s0, s1
; CHECK-HARDFP-SP-NEXT:    mov r0, #0
; CHECK-HARDFP-SP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-SP-NEXT:    movls r0, #1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %cmp = fcmp ole float %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @fcmpge(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fcmpge:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fcmpge
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fcmpge:
; CHECK-SOFTFP:         vmov s2, r0
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vmov s0, r1
; CHECK-SOFTFP-NEXT:    vcmp.f32 s2, s0
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movge r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fcmpge:
; CHECK-HARDFP-SP:         vcmp.f32 s0, s1
; CHECK-HARDFP-SP-NEXT:    mov r0, #0
; CHECK-HARDFP-SP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-SP-NEXT:    movge r0, #1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %cmp = fcmp oge float %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @fcmpgt(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fcmpgt:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fcmpgt
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fcmpgt:
; CHECK-SOFTFP:         vmov s2, r0
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vmov s0, r1
; CHECK-SOFTFP-NEXT:    vcmp.f32 s2, s0
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movgt r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fcmpgt:
; CHECK-HARDFP-SP:         vcmp.f32 s0, s1
; CHECK-HARDFP-SP-NEXT:    mov r0, #0
; CHECK-HARDFP-SP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-SP-NEXT:    movgt r0, #1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %cmp = fcmp ogt float %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @fcmpun(float %a, float %b) #0 {
; CHECK-SOFT-LABEL: fcmpun:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_fcmpun
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: fcmpun:
; CHECK-SOFTFP:         vmov s2, r0
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vmov s0, r1
; CHECK-SOFTFP-NEXT:    vcmp.f32 s2, s0
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movvs r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: fcmpun:
; CHECK-HARDFP-SP:         vcmp.f32 s0, s1
; CHECK-HARDFP-SP-NEXT:    mov r0, #0
; CHECK-HARDFP-SP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-SP-NEXT:    movvs r0, #1
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %cmp = fcmp uno float %a, %b
  %0 = zext i1 %cmp to i32
  ret i32 %0
}

define double @dadd(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dadd:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dadd
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dadd:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    vadd.f64 d16, d17, d16
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dadd:
; CHECK-HARDFP-DP:         vadd.f64 d0, d0, d1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dadd:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dadd
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %add = fadd double %a, %b
  ret double %add
}

define double @ddiv(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: ddiv:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_ddiv
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: ddiv:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    vdiv.f64 d16, d17, d16
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: ddiv:
; CHECK-HARDFP-DP:         vdiv.f64 d0, d0, d1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: ddiv:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_ddiv
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %div = fdiv double %a, %b
  ret double %div
}

define double @dmul(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dmul:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dmul
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dmul:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    vmul.f64 d16, d17, d16
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dmul:
; CHECK-HARDFP-DP:         vmul.f64 d0, d0, d1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dmul:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dmul
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %mul = fmul double %a, %b
  ret double %mul
}

define double @dsub(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dsub:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dsub
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dsub:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    vsub.f64 d16, d17, d16
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dsub:
; CHECK-HARDFP-DP:         vsub.f64 d0, d0, d1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dsub:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dsub
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %sub = fsub double %a, %b
  ret double %sub
}

define i32 @dcmpeq(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dcmpeq:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dcmpeq
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dcmpeq:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vcmp.f64 d17, d16
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    moveq r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dcmpeq:
; CHECK-HARDFP-DP:         vcmp.f64 d0, d1
; CHECK-HARDFP-DP-NEXT:    mov r0, #0
; CHECK-HARDFP-DP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-DP-NEXT:    moveq r0, #1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dcmpeq:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dcmpeq
; CHECK-HARDFP-SPONLY-NEXT:    cmp r0, #0
; CHECK-HARDFP-SPONLY-NEXT:    movne r0, #1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %cmp = fcmp oeq double %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @dcmplt(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dcmplt:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dcmplt
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dcmplt:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vcmp.f64 d17, d16
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movmi r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dcmplt:
; CHECK-HARDFP-DP:         vcmp.f64 d0, d1
; CHECK-HARDFP-DP-NEXT:    mov r0, #0
; CHECK-HARDFP-DP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-DP-NEXT:    movmi r0, #1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dcmplt:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dcmplt
; CHECK-HARDFP-SPONLY-NEXT:    cmp r0, #0
; CHECK-HARDFP-SPONLY-NEXT:    movne r0, #1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %cmp = fcmp olt double %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @dcmple(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dcmple:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dcmple
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dcmple:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vcmp.f64 d17, d16
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movls r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dcmple:
; CHECK-HARDFP-DP:         vcmp.f64 d0, d1
; CHECK-HARDFP-DP-NEXT:    mov r0, #0
; CHECK-HARDFP-DP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-DP-NEXT:    movls r0, #1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dcmple:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dcmple
; CHECK-HARDFP-SPONLY-NEXT:    cmp r0, #0
; CHECK-HARDFP-SPONLY-NEXT:    movne r0, #1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %cmp = fcmp ole double %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @dcmpge(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dcmpge:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dcmpge
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dcmpge:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vcmp.f64 d17, d16
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movge r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dcmpge:
; CHECK-HARDFP-DP:         vcmp.f64 d0, d1
; CHECK-HARDFP-DP-NEXT:    mov r0, #0
; CHECK-HARDFP-DP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-DP-NEXT:    movge r0, #1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dcmpge:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dcmpge
; CHECK-HARDFP-SPONLY-NEXT:    cmp r0, #0
; CHECK-HARDFP-SPONLY-NEXT:    movne r0, #1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %cmp = fcmp oge double %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @dcmpgt(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dcmpgt:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dcmpgt
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dcmpgt:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vcmp.f64 d17, d16
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movgt r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dcmpgt:
; CHECK-HARDFP-DP:         vcmp.f64 d0, d1
; CHECK-HARDFP-DP-NEXT:    mov r0, #0
; CHECK-HARDFP-DP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-DP-NEXT:    movgt r0, #1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dcmpgt:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dcmpgt
; CHECK-HARDFP-SPONLY-NEXT:    cmp r0, #0
; CHECK-HARDFP-SPONLY-NEXT:    movne r0, #1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %cmp = fcmp ogt double %a, %b
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @dcmpun(double %a, double %b) #0 {
; CHECK-SOFT-LABEL: dcmpun:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_dcmpun
; CHECK-SOFT-NEXT:    cmp r0, #0
; CHECK-SOFT-NEXT:    movne r0, #1
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: dcmpun:
; CHECK-SOFTFP:         vmov d16, r2, r3
; CHECK-SOFTFP-NEXT:    vmov d17, r0, r1
; CHECK-SOFTFP-NEXT:    mov r0, #0
; CHECK-SOFTFP-NEXT:    vcmp.f64 d17, d16
; CHECK-SOFTFP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-SOFTFP-NEXT:    movvs r0, #1
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: dcmpun:
; CHECK-HARDFP-DP:         vcmp.f64 d0, d1
; CHECK-HARDFP-DP-NEXT:    mov r0, #0
; CHECK-HARDFP-DP-NEXT:    vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-DP-NEXT:    movvs r0, #1
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: dcmpun:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    vmov r2, r3, d1
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_dcmpun
; CHECK-HARDFP-SPONLY-NEXT:    cmp r0, #0
; CHECK-HARDFP-SPONLY-NEXT:    movne r0, #1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %cmp = fcmp uno double %a, %b
  %0 = zext i1 %cmp to i32
  ret i32 %0
}

define i32 @d2iz(double %a) #0 {
; CHECK-SOFT-LABEL: d2iz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_d2iz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: d2iz:
; CHECK-SOFTFP:         vmov d16, r0, r1
; CHECK-SOFTFP-NEXT:    vcvt.s32.f64 s0, d16
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: d2iz:
; CHECK-HARDFP-DP:         vcvt.s32.f64 s0, d0
; CHECK-HARDFP-DP-NEXT:    vmov r0, s0
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: d2iz:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_d2iz
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %conv = fptosi double %a to i32
  ret i32 %conv
}

define i32 @d2uiz(double %a) #0 {
; CHECK-SOFT-LABEL: d2uiz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_d2uiz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: d2uiz:
; CHECK-SOFTFP:         vmov d16, r0, r1
; CHECK-SOFTFP-NEXT:    vcvt.u32.f64 s0, d16
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: d2uiz:
; CHECK-HARDFP-DP:         vcvt.u32.f64 s0, d0
; CHECK-HARDFP-DP-NEXT:    vmov r0, s0
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: d2uiz:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_d2uiz
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %conv = fptoui double %a to i32
  ret i32 %conv
}

define i64 @d2lz(double %a) #0 {
; CHECK-SOFT-LABEL: d2lz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_d2lz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: d2lz:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_d2lz
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: d2lz:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_d2lz
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = fptosi double %a to i64
  ret i64 %conv
}

define i64 @d2ulz(double %a) #0 {
; CHECK-SOFT-LABEL: d2ulz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_d2ulz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: d2ulz:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_d2ulz
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: d2ulz:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_d2ulz
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = fptoui double %a to i64
  ret i64 %conv
}

define i32 @f2iz(float %a) #0 {
; CHECK-SOFT-LABEL: f2iz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_f2iz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: f2iz:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.s32.f32 s0, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: f2iz:
; CHECK-HARDFP-SP:         vcvt.s32.f32 s0, s0
; CHECK-HARDFP-SP-NEXT:    vmov r0, s0
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = fptosi float %a to i32
  ret i32 %conv
}

define i32 @f2uiz(float %a) #0 {
; CHECK-SOFT-LABEL: f2uiz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_f2uiz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: f2uiz:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.u32.f32 s0, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: f2uiz:
; CHECK-HARDFP-SP:         vcvt.u32.f32 s0, s0
; CHECK-HARDFP-SP-NEXT:    vmov r0, s0
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = fptoui float %a to i32
  ret i32 %conv
}

define i64 @f2lz(float %a) #0 {
; CHECK-SOFT-LABEL: f2lz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_f2lz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: f2lz:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_f2lz
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: f2lz:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    vmov r0, s0
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_f2lz
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = fptosi float %a to i64
  ret i64 %conv
}

define i64 @f2ulz(float %a) #0 {
; CHECK-SOFT-LABEL: f2ulz:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_f2ulz
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: f2ulz:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_f2ulz
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: f2ulz:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    vmov r0, s0
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_f2ulz
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = fptoui float %a to i64
  ret i64 %conv
}

define float @d2f(double %a) #0 {
; CHECK-SOFT-LABEL: d2f:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_d2f
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: d2f:
; CHECK-SOFTFP:         vmov d16, r0, r1
; CHECK-SOFTFP-NEXT:    vcvt.f32.f64 s0, d16
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: d2f:
; CHECK-HARDFP-DP:         vcvt.f32.f64 s0, d0
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: d2f:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, r1, d0
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_d2f
; CHECK-HARDFP-SPONLY-NEXT:    vmov s0, r0
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %conv = fptrunc double %a to float
  ret float %conv
}

define double @f2d(float %a) #0 {
; CHECK-SOFT-LABEL: f2d:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_f2d
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: f2d:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.f64.f32 d16, s0
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: f2d:
; CHECK-HARDFP-DP:         vcvt.f64.f32 d0, s0
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: f2d:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    vmov r0, s0
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_f2d
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %conv = fpext float %a to double
  ret double %conv
}

define double @i2d(i32 %a) #0 {
; CHECK-SOFT-LABEL: i2d:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_i2d
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: i2d:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.f64.s32 d16, s0
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: i2d:
; CHECK-HARDFP-DP:         vmov s0, r0
; CHECK-HARDFP-DP-NEXT:    vcvt.f64.s32 d0, s0
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: i2d:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_i2d
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %conv = sitofp i32 %a to double
  ret double %conv
}

define double @ui2d(i32 %a) #0 {
; CHECK-SOFT-LABEL: ui2d:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_ui2d
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: ui2d:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.f64.u32 d16, s0
; CHECK-SOFTFP-NEXT:    vmov r0, r1, d16
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-DP-LABEL: ui2d:
; CHECK-HARDFP-DP:         vmov s0, r0
; CHECK-HARDFP-DP-NEXT:    vcvt.f64.u32 d0, s0
; CHECK-HARDFP-DP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SPONLY-LABEL: ui2d:
; CHECK-HARDFP-SPONLY:         .save {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    push {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    bl __aeabi_ui2d
; CHECK-HARDFP-SPONLY-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SPONLY-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SPONLY-NEXT:    mov pc, lr
entry:
  %conv = uitofp i32 %a to double
  ret double %conv
}

define double @l2d(i64 %a) #0 {
; CHECK-SOFT-LABEL: l2d:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_l2d
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: l2d:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_l2d
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: l2d:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_l2d
; CHECK-HARDFP-SP-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = sitofp i64 %a to double
  ret double %conv
}

define double @ul2d(i64 %a) #0 {
; CHECK-SOFT-LABEL: ul2d:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_ul2d
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: ul2d:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_ul2d
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: ul2d:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_ul2d
; CHECK-HARDFP-SP-NEXT:    vmov d0, r0, r1
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = uitofp i64 %a to double
  ret double %conv
}

define float @i2f(i32 %a) #0 {
; CHECK-SOFT-LABEL: i2f:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_i2f
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: i2f:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.f32.s32 s0, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: i2f:
; CHECK-HARDFP-SP:         vmov s0, r0
; CHECK-HARDFP-SP-NEXT:    vcvt.f32.s32 s0, s0
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = sitofp i32 %a to float
  ret float %conv
}

define float @ui2f(i32 %a) #0 {
; CHECK-SOFT-LABEL: ui2f:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_ui2f
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: ui2f:
; CHECK-SOFTFP:         vmov s0, r0
; CHECK-SOFTFP-NEXT:    vcvt.f32.u32 s0, s0
; CHECK-SOFTFP-NEXT:    vmov r0, s0
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: ui2f:
; CHECK-HARDFP-SP:         vmov s0, r0
; CHECK-HARDFP-SP-NEXT:    vcvt.f32.u32 s0, s0
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = uitofp i32 %a to float
  ret float %conv
}

define float @l2f(i64 %a) #0 {
; CHECK-SOFT-LABEL: l2f:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_l2f
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: l2f:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_l2f
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: l2f:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_l2f
; CHECK-HARDFP-SP-NEXT:    vmov s0, r0
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = sitofp i64 %a to float
  ret float %conv
}

define float @ul2f(i64 %a) #0 {
; CHECK-SOFT-LABEL: ul2f:
; CHECK-SOFT:         .save {r11, lr}
; CHECK-SOFT-NEXT:    push {r11, lr}
; CHECK-SOFT-NEXT:    bl __aeabi_ul2f
; CHECK-SOFT-NEXT:    pop {r11, lr}
; CHECK-SOFT-NEXT:    mov pc, lr
;
; CHECK-SOFTFP-LABEL: ul2f:
; CHECK-SOFTFP:         .save {r11, lr}
; CHECK-SOFTFP-NEXT:    push {r11, lr}
; CHECK-SOFTFP-NEXT:    bl __aeabi_ul2f
; CHECK-SOFTFP-NEXT:    pop {r11, lr}
; CHECK-SOFTFP-NEXT:    mov pc, lr
;
; CHECK-HARDFP-SP-LABEL: ul2f:
; CHECK-HARDFP-SP:         .save {r11, lr}
; CHECK-HARDFP-SP-NEXT:    push {r11, lr}
; CHECK-HARDFP-SP-NEXT:    bl __aeabi_ul2f
; CHECK-HARDFP-SP-NEXT:    vmov s0, r0
; CHECK-HARDFP-SP-NEXT:    pop {r11, lr}
; CHECK-HARDFP-SP-NEXT:    mov pc, lr
entry:
  %conv = uitofp i64 %a to float
  ret float %conv
}
attributes #0 = { nounwind }