bf16-create-get-set-dup.ll
5.88 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv8.6a-arm-none-eabi -mattr=+bf16,+neon,fullfp16 < %s | FileCheck %s
; FIXME: Remove fullfp16 once bfloat arguments and returns lowering stops
; depending on it.
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8.6a-arm-none-eabi"
define arm_aapcs_vfpcc <4 x bfloat> @test_vcreate_bf16(i64 %a) {
; CHECK-LABEL: test_vcreate_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d0, r0, r1
; CHECK-NEXT: bx lr
entry:
%0 = bitcast i64 %a to <4 x bfloat>
ret <4 x bfloat> %0
}
define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_n_bf16(bfloat %v) {
; CHECK-LABEL: test_vdup_n_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d0
; CHECK-NEXT: vdup.16 d0, d0[0]
; CHECK-NEXT: bx lr
entry:
%vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 0
%vecinit3.i = shufflevector <4 x bfloat> %vecinit.i, <4 x bfloat> undef, <4 x i32> zeroinitializer
ret <4 x bfloat> %vecinit3.i
}
define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_n_bf16(bfloat %v) {
; CHECK-LABEL: test_vdupq_n_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d0
; CHECK-NEXT: vdup.16 q0, d0[0]
; CHECK-NEXT: bx lr
entry:
%vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 0
%vecinit7.i = shufflevector <8 x bfloat> %vecinit.i, <8 x bfloat> undef, <8 x i32> zeroinitializer
ret <8 x bfloat> %vecinit7.i
}
define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> %v) {
; CHECK-LABEL: test_vdup_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vdup.16 d0, d0[1]
; CHECK-NEXT: bx lr
entry:
%lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
ret <4 x bfloat> %lane
}
define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> %v) {
; CHECK-LABEL: test_vdupq_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: vdup.16 q0, d0[1]
; CHECK-NEXT: bx lr
entry:
%lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
ret <8 x bfloat> %lane
}
define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> %v) {
; CHECK-LABEL: test_vdup_laneq_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vdup.16 d0, d1[3]
; CHECK-NEXT: bx lr
entry:
%lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
ret <4 x bfloat> %lane
}
define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> %v) {
; CHECK-LABEL: test_vdupq_laneq_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vdup.16 q0, d1[3]
; CHECK-NEXT: bx lr
entry:
%lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <8 x bfloat> %lane
}
define arm_aapcs_vfpcc <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> %low, <4 x bfloat> %high) {
; CHECK-LABEL: test_vcombine_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f64 d16, d1
; CHECK-NEXT: vorr d17, d0, d0
; CHECK-NEXT: vorr q0, q8, q8
; CHECK-NEXT: bx lr
entry:
%shuffle.i = shufflevector <4 x bfloat> %high, <4 x bfloat> %low, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x bfloat> %shuffle.i
}
define arm_aapcs_vfpcc <4 x bfloat> @test_vget_high_bf16(<8 x bfloat> %a) {
; CHECK-LABEL: test_vget_high_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f64 d0, d1
; CHECK-NEXT: bx lr
entry:
%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
ret <4 x bfloat> %shuffle.i
}
define arm_aapcs_vfpcc <4 x bfloat> @test_vget_low_bf16(<8 x bfloat> %a) {
; CHECK-LABEL: test_vget_low_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: bx lr
entry:
%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x bfloat> %shuffle.i
}
define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_even(<8 x bfloat> %v) {
; CHECK-LABEL: test_vgetq_lane_bf16_even:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s0, s3
; CHECK-NEXT: bx lr
entry:
%0 = extractelement <8 x bfloat> %v, i32 6
ret bfloat %0
}
define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_odd(<8 x bfloat> %v) {
; CHECK-LABEL: test_vgetq_lane_bf16_odd:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: bx lr
entry:
%0 = extractelement <8 x bfloat> %v, i32 7
ret bfloat %0
}
define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_even(<4 x bfloat> %v) {
; CHECK-LABEL: test_vget_lane_bf16_even:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: bx lr
entry:
%0 = extractelement <4 x bfloat> %v, i32 2
ret bfloat %0
}
define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_odd(<4 x bfloat> %v) {
; CHECK-LABEL: test_vget_lane_bf16_odd:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: bx lr
entry:
%0 = extractelement <4 x bfloat> %v, i32 1
ret bfloat %0
}
define arm_aapcs_vfpcc <4 x bfloat> @test_vset_lane_bf16(bfloat %a, <4 x bfloat> %v) {
; CHECK-LABEL: test_vset_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 d1[1], r0
; CHECK-NEXT: vorr d0, d1, d1
; CHECK-NEXT: bx lr
entry:
%0 = insertelement <4 x bfloat> %v, bfloat %a, i32 1
ret <4 x bfloat> %0
}
define arm_aapcs_vfpcc <8 x bfloat> @test_vsetq_lane_bf16(bfloat %a, <8 x bfloat> %v) {
; CHECK-LABEL: test_vsetq_lane_bf16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 d3[3], r0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: bx lr
entry:
%0 = insertelement <8 x bfloat> %v, bfloat %a, i32 7
ret <8 x bfloat> %0
}