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Syntax of Core GFX7 Instructions
====================================================================================
.. contents::
:local:
Introduction
============
This document describes the syntax of *core* GFX7 instructions.
Notation
========
Notation used in this document is explained :ref:`here`.
Overview
========
An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document`.
Instructions
============
DS
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_add_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_add_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_and_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_and_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_append :ref:`vdst` :ref:`offset16` :ref:`gds`
ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_consume :ref:`vdst` :ref:`offset16` :ref:`gds`
ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_dec_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_dec_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_gws_barrier :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_gws_init :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_gws_sema_br :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_gws_sema_p :ref:`offset16` :ref:`gds`
ds_gws_sema_release_all :ref:`offset16` :ref:`gds`
ds_gws_sema_v :ref:`offset16` :ref:`gds`
ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_inc_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_inc_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_max_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_max_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_max_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_max_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_max_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_min_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_min_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_min_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_min_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_min_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_nop
ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_or_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_or_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_sub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_sub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds`
ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds`
ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_write_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_write_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds`
ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds`
ds_xor_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds`
ds_xor_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds`
EXP
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm`
FLAT
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc`
flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc`
flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc`
flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc`
flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`glc` :ref:`slc`
flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`glc` :ref:`slc`
flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc`
flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc`
flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc`
flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc`
flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc`
flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc`
flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`glc` :ref:`slc`
flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`glc` :ref:`slc`
flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`glc` :ref:`slc`
flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`glc` :ref:`slc`
flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc`
flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc`
flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc`
flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc`
flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc`
flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc`
MIMG
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
MTBUF
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
MUBUF
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds`
buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds`
buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds`
buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds`
buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds`
buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds`
buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc`
buffer_wbinvl1
buffer_wbinvl1_vol
SMRD
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_dcache_inv
s_dcache_inv_vol
s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset`
s_memtime :ref:`sdst`
SOP1
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_abs_i32 :ref:`sdst`, :ref:`ssrc`
s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc`
s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc`
s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc`
s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc`
s_bitset0_b32 :ref:`sdst`, :ref:`ssrc`
s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32`
s_bitset1_b32 :ref:`sdst`, :ref:`ssrc`
s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32`
s_brev_b32 :ref:`sdst`, :ref:`ssrc`
s_brev_b64 :ref:`sdst`, :ref:`ssrc`
s_cbranch_join :ref:`ssrc`
s_cmov_b32 :ref:`sdst`, :ref:`ssrc`
s_cmov_b64 :ref:`sdst`, :ref:`ssrc`
s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc`
s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc`
s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc`
s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc`
s_flbit_i32 :ref:`sdst`, :ref:`ssrc`
s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc`
s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc`
s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc`
s_getpc_b64 :ref:`sdst`
s_mov_b32 :ref:`sdst`, :ref:`ssrc`
s_mov_b64 :ref:`sdst`, :ref:`ssrc`
s_movreld_b32 :ref:`sdst`, :ref:`ssrc`
s_movreld_b64 :ref:`sdst`, :ref:`ssrc`
s_movrels_b32 :ref:`sdst`, :ref:`ssrc`
s_movrels_b64 :ref:`sdst`, :ref:`ssrc`
s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_not_b32 :ref:`sdst`, :ref:`ssrc`
s_not_b64 :ref:`sdst`, :ref:`ssrc`
s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_quadmask_b32 :ref:`sdst`, :ref:`ssrc`
s_quadmask_b64 :ref:`sdst`, :ref:`ssrc`
s_rfe_b64 :ref:`ssrc`
s_setpc_b64 :ref:`ssrc`
s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc`
s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc`
s_swappc_b64 :ref:`sdst`, :ref:`ssrc`
s_wqm_b32 :ref:`sdst`, :ref:`ssrc`
s_wqm_b64 :ref:`sdst`, :ref:`ssrc`
s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc`
SOP2
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32`
s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1`
s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`
SOPC
-----------------------
.. parsed-literal::
**INSTRUCTION** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1`
s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1`
s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32`
s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1`
s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1`
s_setvskip :ref:`ssrc0`, :ref:`ssrc1`
SOPK
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_addk_i32 :ref:`sdst`, :ref:`imm16`
s_cbranch_i_fork :ref:`ssrc`, :ref:`label`
s_cmovk_i32 :ref:`sdst`, :ref:`imm16`
s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16`
s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16`
s_getreg_b32 :ref:`sdst`, :ref:`hwreg`
s_movk_i32 :ref:`sdst`, :ref:`imm16`
s_mulk_i32 :ref:`sdst`, :ref:`imm16`
s_setreg_b32 :ref:`hwreg`, :ref:`ssrc`
s_setreg_imm32_b32 :ref:`hwreg`, :ref:`imm32`
SOPP
-----------------------
.. parsed-literal::
**INSTRUCTION** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_barrier
s_branch :ref:`label`
s_cbranch_cdbgsys :ref:`label`
s_cbranch_cdbgsys_and_user :ref:`label`
s_cbranch_cdbgsys_or_user :ref:`label`
s_cbranch_cdbguser :ref:`label`
s_cbranch_execnz :ref:`label`
s_cbranch_execz :ref:`label`
s_cbranch_scc0 :ref:`label`
s_cbranch_scc1 :ref:`label`
s_cbranch_vccnz :ref:`label`
s_cbranch_vccz :ref:`label`
s_decperflevel :ref:`imm16`
s_endpgm
s_icache_inv
s_incperflevel :ref:`imm16`
s_nop :ref:`imm16`
s_sendmsg :ref:`msg`
s_sendmsghalt :ref:`msg`
s_sethalt :ref:`imm16`
s_setkill :ref:`imm16`
s_setprio :ref:`imm16`
s_sleep :ref:`imm16`
s_trap :ref:`imm16`
s_ttracedata
s_waitcnt :ref:`waitcnt`
VINTRP
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32`
v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32`
v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32`
VOP1
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_bfrev_b32 :ref:`vdst`, :ref:`src`
v_ceil_f32 :ref:`vdst`, :ref:`src`
v_ceil_f64 :ref:`vdst`, :ref:`src`
v_clrexcp
v_cos_f32 :ref:`vdst`, :ref:`src`
v_cvt_f16_f32 :ref:`vdst`, :ref:`src`
v_cvt_f32_f16 :ref:`vdst`, :ref:`src`
v_cvt_f32_f64 :ref:`vdst`, :ref:`src`
v_cvt_f32_i32 :ref:`vdst`, :ref:`src`
v_cvt_f32_u32 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src`
v_cvt_f64_f32 :ref:`vdst`, :ref:`src`
v_cvt_f64_i32 :ref:`vdst`, :ref:`src`
v_cvt_f64_u32 :ref:`vdst`, :ref:`src`
v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src`
v_cvt_i32_f32 :ref:`vdst`, :ref:`src`
v_cvt_i32_f64 :ref:`vdst`, :ref:`src`
v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src`
v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src`
v_cvt_u32_f32 :ref:`vdst`, :ref:`src`
v_cvt_u32_f64 :ref:`vdst`, :ref:`src`
v_exp_f32 :ref:`vdst`, :ref:`src`
v_exp_legacy_f32 :ref:`vdst`, :ref:`src`
v_ffbh_i32 :ref:`vdst`, :ref:`src`
v_ffbh_u32 :ref:`vdst`, :ref:`src`
v_ffbl_b32 :ref:`vdst`, :ref:`src`
v_floor_f32 :ref:`vdst`, :ref:`src`
v_floor_f64 :ref:`vdst`, :ref:`src`
v_fract_f32 :ref:`vdst`, :ref:`src`
v_fract_f64 :ref:`vdst`, :ref:`src`
v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src`
v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src`
v_frexp_mant_f32 :ref:`vdst`, :ref:`src`
v_frexp_mant_f64 :ref:`vdst`, :ref:`src`
v_log_clamp_f32 :ref:`vdst`, :ref:`src`
v_log_f32 :ref:`vdst`, :ref:`src`
v_log_legacy_f32 :ref:`vdst`, :ref:`src`
v_mov_b32 :ref:`vdst`, :ref:`src`
v_movreld_b32 :ref:`vdst`, :ref:`src`
v_movrels_b32 :ref:`vdst`, :ref:`vsrc`
v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc`
v_nop
v_not_b32 :ref:`vdst`, :ref:`src`
v_rcp_clamp_f32 :ref:`vdst`, :ref:`src`
v_rcp_clamp_f64 :ref:`vdst`, :ref:`src`
v_rcp_f32 :ref:`vdst`, :ref:`src`
v_rcp_f64 :ref:`vdst`, :ref:`src`
v_rcp_iflag_f32 :ref:`vdst`, :ref:`src`
v_rcp_legacy_f32 :ref:`vdst`, :ref:`src`
v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc`
v_rndne_f32 :ref:`vdst`, :ref:`src`
v_rndne_f64 :ref:`vdst`, :ref:`src`
v_rsq_clamp_f32 :ref:`vdst`, :ref:`src`
v_rsq_clamp_f64 :ref:`vdst`, :ref:`src`
v_rsq_f32 :ref:`vdst`, :ref:`src`
v_rsq_f64 :ref:`vdst`, :ref:`src`
v_rsq_legacy_f32 :ref:`vdst`, :ref:`src`
v_sin_f32 :ref:`vdst`, :ref:`src`
v_sqrt_f32 :ref:`vdst`, :ref:`src`
v_sqrt_f64 :ref:`vdst`, :ref:`src`
v_trunc_f32 :ref:`vdst`, :ref:`src`
v_trunc_f64 :ref:`vdst`, :ref:`src`
VOP2
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_add_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc`
v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_ashr_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32`
v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1`
v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc`
v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_cvt_pkaccum_u8_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32`
v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_ldexp_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i32`
v_lshl_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32`
v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1`
v_lshr_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32`
v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1`
v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32`
v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2`
v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_max_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_min_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1`
v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_sub_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc`
v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc`
v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
v_subrev_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1`
v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`
VOP3
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_add_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2`
v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_ashr_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`
v_ashr_i64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`
v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`
v_bcnt_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32`
v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_bfm_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_bfrev_b32_e64 :ref:`vdst`, :ref:`src`
v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_clrexcp_e64
v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32`
v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32`
v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmps_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpsx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32`
v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32`
v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2`
v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod`
v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod`
v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod`
v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src`
v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src`
v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod`
v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod`
v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod`
v_cvt_pk_i16_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_cvt_pk_u16_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_cvt_pk_u8_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32`
v_cvt_pkaccum_u8_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32`
v_cvt_pknorm_i16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cvt_pknorm_u16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`
v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_ffbh_i32_e64 :ref:`vdst`, :ref:`src`
v_ffbh_u32_e64 :ref:`vdst`, :ref:`src`
v_ffbl_b32_e64 :ref:`vdst`, :ref:`src`
v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`
v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m`
v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`
v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_ldexp_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod`
v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod`
v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32`
v_log_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_lshl_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`
v_lshl_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`
v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`
v_lshr_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`
v_lshr_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`
v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`
v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32`
v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64`
v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32`
v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64`
v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_max_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mbcnt_hi_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mbcnt_lo_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_min_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mov_b32_e64 :ref:`vdst`, :ref:`src`
v_movreld_b32_e64 :ref:`vdst`, :ref:`src`
v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc`
v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc`
v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64`
v_mqsad_u32_u8 :ref:`vdst`::ref:`b128`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`vsrc2`::ref:`b128`
v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32`
v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_mul_lo_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod`
v_nop_e64
v_not_b32_e64 :ref:`vdst`, :ref:`src`
v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
v_qsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64`
v_rcp_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rcp_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rcp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rsq_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rsq_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_rsq_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32`
v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32`
v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`
v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32`
v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_sub_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2`
v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2`
v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod`
v_subrev_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`
v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod`
v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod`
v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`
VOPC
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32`
v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32`
v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmps_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpsx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32`
v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32`
v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`
.. |---| unicode:: U+02014 .. em dash
.. toctree::
:hidden:
gfx7_attr
gfx7_bimm16
gfx7_bimm32
gfx7_fimm32
gfx7_hwreg
gfx7_label
gfx7_msg
gfx7_param
gfx7_simm16
gfx7_tgt
gfx7_uimm16
gfx7_waitcnt
gfx7_addr_buf
gfx7_addr_ds
gfx7_addr_flat
gfx7_addr_mimg
gfx7_base_smem_addr
gfx7_base_smem_buf
gfx7_data_buf_atomic128
gfx7_data_buf_atomic32
gfx7_data_buf_atomic64
gfx7_data_mimg_atomic_cmp
gfx7_data_mimg_atomic_reg
gfx7_data_mimg_store
gfx7_dst_buf_128
gfx7_dst_buf_32
gfx7_dst_buf_64
gfx7_dst_buf_96
gfx7_dst_buf_lds
gfx7_dst_flat_atomic32
gfx7_dst_flat_atomic64
gfx7_dst_mimg_gather4
gfx7_dst_mimg_regular
gfx7_offset_buf
gfx7_offset_smem
gfx7_rsrc_buf
gfx7_rsrc_mimg
gfx7_samp_mimg
gfx7_sdst128_0
gfx7_sdst256_0
gfx7_sdst32_0
gfx7_sdst32_1
gfx7_sdst32_2
gfx7_sdst512_0
gfx7_sdst64_0
gfx7_sdst64_1
gfx7_src32_0
gfx7_src32_1
gfx7_src32_2
gfx7_src32_3
gfx7_src32_4
gfx7_src32_5
gfx7_src32_6
gfx7_src64_0
gfx7_src64_1
gfx7_src64_2
gfx7_src_exp
gfx7_ssrc32_0
gfx7_ssrc32_1
gfx7_ssrc32_2
gfx7_ssrc32_3
gfx7_ssrc32_4
gfx7_ssrc32_5
gfx7_ssrc32_6
gfx7_ssrc64_0
gfx7_ssrc64_1
gfx7_ssrc64_2
gfx7_ssrc64_3
gfx7_vcc_64
gfx7_vdata128_0
gfx7_vdata32_0
gfx7_vdata64_0
gfx7_vdata96_0
gfx7_vdst128_0
gfx7_vdst32_0
gfx7_vdst64_0
gfx7_vdst96_0
gfx7_vsrc128_0
gfx7_vsrc32_0
gfx7_vsrc32_1
gfx7_vsrc64_0
gfx7_mod
gfx7_opt
gfx7_ret
gfx7_type_dev