MachineInstrTest.cpp
28.6 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
#include "ARMBaseInstrInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "gtest/gtest.h"
using namespace llvm;
TEST(MachineInstructionDoubleWidthResult, IsCorrect) {
using namespace ARM;
auto DoubleWidthResult = [](unsigned Opcode) {
switch (Opcode) {
default:
break;
case MVE_VMULLBp16:
case MVE_VMULLBp8:
case MVE_VMULLBs16:
case MVE_VMULLBs32:
case MVE_VMULLBs8:
case MVE_VMULLBu16:
case MVE_VMULLBu32:
case MVE_VMULLBu8:
case MVE_VMULLTp16:
case MVE_VMULLTp8:
case MVE_VMULLTs16:
case MVE_VMULLTs32:
case MVE_VMULLTs8:
case MVE_VMULLTu16:
case MVE_VMULLTu32:
case MVE_VMULLTu8:
case MVE_VQDMULL_qr_s16bh:
case MVE_VQDMULL_qr_s16th:
case MVE_VQDMULL_qr_s32bh:
case MVE_VQDMULL_qr_s32th:
case MVE_VQDMULLs16bh:
case MVE_VQDMULLs16th:
case MVE_VQDMULLs32bh:
case MVE_VQDMULLs32th:
case MVE_VMOVLs16bh:
case MVE_VMOVLs16th:
case MVE_VMOVLs8bh:
case MVE_VMOVLs8th:
case MVE_VMOVLu16bh:
case MVE_VMOVLu16th:
case MVE_VMOVLu8bh:
case MVE_VMOVLu8th:
case MVE_VSHLL_imms16bh:
case MVE_VSHLL_imms16th:
case MVE_VSHLL_imms8bh:
case MVE_VSHLL_imms8th:
case MVE_VSHLL_immu16bh:
case MVE_VSHLL_immu16th:
case MVE_VSHLL_immu8bh:
case MVE_VSHLL_immu8th:
case MVE_VSHLL_lws16bh:
case MVE_VSHLL_lws16th:
case MVE_VSHLL_lws8bh:
case MVE_VSHLL_lws8th:
case MVE_VSHLL_lwu16bh:
case MVE_VSHLL_lwu16th:
case MVE_VSHLL_lwu8bh:
case MVE_VSHLL_lwu8th:
return true;
}
return false;
};
LLVMInitializeARMTargetInfo();
LLVMInitializeARMTarget();
LLVMInitializeARMTargetMC();
auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
std::string Error;
const Target *T = TargetRegistry::lookupTarget(TT, Error);
if (!T) {
dbgs() << Error;
return;
}
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine*>(
T->createTargetMachine(TT, "generic", "", Options, None, None,
CodeGenOpt::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
const ARMBaseInstrInfo *TII = ST.getInstrInfo();
auto MII = TM->getMCInstrInfo();
for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
const MCInstrDesc &Desc = TII->get(i);
uint64_t Flags = Desc.TSFlags;
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
continue;
bool Valid = (Flags & ARMII::DoubleWidthResult) != 0;
ASSERT_EQ(DoubleWidthResult(i), Valid)
<< MII->getName(i)
<< ": mismatched expectation for tail-predicated safety\n";
}
}
TEST(MachineInstructionHorizontalReduction, IsCorrect) {
using namespace ARM;
auto HorizontalReduction = [](unsigned Opcode) {
switch (Opcode) {
default:
break;
case MVE_VABAVs16:
case MVE_VABAVs32:
case MVE_VABAVs8:
case MVE_VABAVu16:
case MVE_VABAVu32:
case MVE_VABAVu8:
case MVE_VADDLVs32acc:
case MVE_VADDLVs32no_acc:
case MVE_VADDLVu32acc:
case MVE_VADDLVu32no_acc:
case MVE_VADDVs16acc:
case MVE_VADDVs16no_acc:
case MVE_VADDVs32acc:
case MVE_VADDVs32no_acc:
case MVE_VADDVs8acc:
case MVE_VADDVs8no_acc:
case MVE_VADDVu16acc:
case MVE_VADDVu16no_acc:
case MVE_VADDVu32acc:
case MVE_VADDVu32no_acc:
case MVE_VADDVu8acc:
case MVE_VADDVu8no_acc:
case MVE_VMAXAVs16:
case MVE_VMAXAVs32:
case MVE_VMAXAVs8:
case MVE_VMAXNMAVf16:
case MVE_VMAXNMAVf32:
case MVE_VMAXNMVf16:
case MVE_VMAXNMVf32:
case MVE_VMAXVs16:
case MVE_VMAXVs32:
case MVE_VMAXVs8:
case MVE_VMAXVu16:
case MVE_VMAXVu32:
case MVE_VMAXVu8:
case MVE_VMINAVs16:
case MVE_VMINAVs32:
case MVE_VMINAVs8:
case MVE_VMINNMAVf16:
case MVE_VMINNMAVf32:
case MVE_VMINNMVf16:
case MVE_VMINNMVf32:
case MVE_VMINVs16:
case MVE_VMINVs32:
case MVE_VMINVs8:
case MVE_VMINVu16:
case MVE_VMINVu32:
case MVE_VMINVu8:
case MVE_VMLADAVas16:
case MVE_VMLADAVas32:
case MVE_VMLADAVas8:
case MVE_VMLADAVau16:
case MVE_VMLADAVau32:
case MVE_VMLADAVau8:
case MVE_VMLADAVaxs16:
case MVE_VMLADAVaxs32:
case MVE_VMLADAVaxs8:
case MVE_VMLADAVs16:
case MVE_VMLADAVs32:
case MVE_VMLADAVs8:
case MVE_VMLADAVu16:
case MVE_VMLADAVu32:
case MVE_VMLADAVu8:
case MVE_VMLADAVxs16:
case MVE_VMLADAVxs32:
case MVE_VMLADAVxs8:
case MVE_VMLALDAVas16:
case MVE_VMLALDAVas32:
case MVE_VMLALDAVau16:
case MVE_VMLALDAVau32:
case MVE_VMLALDAVaxs16:
case MVE_VMLALDAVaxs32:
case MVE_VMLALDAVs16:
case MVE_VMLALDAVs32:
case MVE_VMLALDAVu16:
case MVE_VMLALDAVu32:
case MVE_VMLALDAVxs16:
case MVE_VMLALDAVxs32:
case MVE_VMLSDAVas16:
case MVE_VMLSDAVas32:
case MVE_VMLSDAVas8:
case MVE_VMLSDAVaxs16:
case MVE_VMLSDAVaxs32:
case MVE_VMLSDAVaxs8:
case MVE_VMLSDAVs16:
case MVE_VMLSDAVs32:
case MVE_VMLSDAVs8:
case MVE_VMLSDAVxs16:
case MVE_VMLSDAVxs32:
case MVE_VMLSDAVxs8:
case MVE_VMLSLDAVas16:
case MVE_VMLSLDAVas32:
case MVE_VMLSLDAVaxs16:
case MVE_VMLSLDAVaxs32:
case MVE_VMLSLDAVs16:
case MVE_VMLSLDAVs32:
case MVE_VMLSLDAVxs16:
case MVE_VMLSLDAVxs32:
case MVE_VRMLALDAVHas32:
case MVE_VRMLALDAVHau32:
case MVE_VRMLALDAVHaxs32:
case MVE_VRMLALDAVHs32:
case MVE_VRMLALDAVHu32:
case MVE_VRMLALDAVHxs32:
case MVE_VRMLSLDAVHas32:
case MVE_VRMLSLDAVHaxs32:
case MVE_VRMLSLDAVHs32:
case MVE_VRMLSLDAVHxs32:
return true;
}
return false;
};
LLVMInitializeARMTargetInfo();
LLVMInitializeARMTarget();
LLVMInitializeARMTargetMC();
auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
std::string Error;
const Target *T = TargetRegistry::lookupTarget(TT, Error);
if (!T) {
dbgs() << Error;
return;
}
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine*>(
T->createTargetMachine(TT, "generic", "", Options, None, None,
CodeGenOpt::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
const ARMBaseInstrInfo *TII = ST.getInstrInfo();
auto MII = TM->getMCInstrInfo();
for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
const MCInstrDesc &Desc = TII->get(i);
uint64_t Flags = Desc.TSFlags;
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
continue;
bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
ASSERT_EQ(HorizontalReduction(i), Valid)
<< MII->getName(i)
<< ": mismatched expectation for tail-predicated safety\n";
}
}
TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
using namespace ARM;
auto RetainsPreviousHalfElement = [](unsigned Opcode) {
switch (Opcode) {
default:
break;
case MVE_VMOVNi16bh:
case MVE_VMOVNi16th:
case MVE_VMOVNi32bh:
case MVE_VMOVNi32th:
case MVE_VQMOVNs16bh:
case MVE_VQMOVNs16th:
case MVE_VQMOVNs32bh:
case MVE_VQMOVNs32th:
case MVE_VQMOVNu16bh:
case MVE_VQMOVNu16th:
case MVE_VQMOVNu32bh:
case MVE_VQMOVNu32th:
case MVE_VQMOVUNs16bh:
case MVE_VQMOVUNs16th:
case MVE_VQMOVUNs32bh:
case MVE_VQMOVUNs32th:
case MVE_VQRSHRNbhs16:
case MVE_VQRSHRNbhs32:
case MVE_VQRSHRNbhu16:
case MVE_VQRSHRNbhu32:
case MVE_VQRSHRNths16:
case MVE_VQRSHRNths32:
case MVE_VQRSHRNthu16:
case MVE_VQRSHRNthu32:
case MVE_VQRSHRUNs16bh:
case MVE_VQRSHRUNs16th:
case MVE_VQRSHRUNs32bh:
case MVE_VQRSHRUNs32th:
case MVE_VQSHRNbhs16:
case MVE_VQSHRNbhs32:
case MVE_VQSHRNbhu16:
case MVE_VQSHRNbhu32:
case MVE_VQSHRNths16:
case MVE_VQSHRNths32:
case MVE_VQSHRNthu16:
case MVE_VQSHRNthu32:
case MVE_VQSHRUNs16bh:
case MVE_VQSHRUNs16th:
case MVE_VQSHRUNs32bh:
case MVE_VQSHRUNs32th:
case MVE_VRSHRNi16bh:
case MVE_VRSHRNi16th:
case MVE_VRSHRNi32bh:
case MVE_VRSHRNi32th:
case MVE_VSHRNi16bh:
case MVE_VSHRNi16th:
case MVE_VSHRNi32bh:
case MVE_VSHRNi32th:
case MVE_VCVTf16f32bh:
case MVE_VCVTf16f32th:
case MVE_VCVTf32f16bh:
case MVE_VCVTf32f16th:
return true;
}
return false;
};
LLVMInitializeARMTargetInfo();
LLVMInitializeARMTarget();
LLVMInitializeARMTargetMC();
auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
std::string Error;
const Target *T = TargetRegistry::lookupTarget(TT, Error);
if (!T) {
dbgs() << Error;
return;
}
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine*>(
T->createTargetMachine(TT, "generic", "", Options, None, None,
CodeGenOpt::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
const ARMBaseInstrInfo *TII = ST.getInstrInfo();
auto MII = TM->getMCInstrInfo();
for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
const MCInstrDesc &Desc = TII->get(i);
uint64_t Flags = Desc.TSFlags;
if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
continue;
bool Valid = (Flags & ARMII::RetainsPreviousHalfElement) != 0;
ASSERT_EQ(RetainsPreviousHalfElement(i), Valid)
<< MII->getName(i)
<< ": mismatched expectation for tail-predicated safety\n";
}
}
// Test for instructions that aren't immediately obviously valid within a
// tail-predicated loop. This should be marked up in their tablegen
// descriptions. Currently we, conservatively, disallow:
// - cross beat carries.
// - complex operations.
// - horizontal operations with exchange.
// - byte swapping.
// - interleaved memory instructions.
// TODO: Add to this list once we can handle them safely.
TEST(MachineInstrValidTailPredication, IsCorrect) {
using namespace ARM;
auto IsValidTPOpcode = [](unsigned Opcode) {
switch (Opcode) {
default:
return false;
case MVE_ASRLi:
case MVE_ASRLr:
case MVE_LSRL:
case MVE_SQRSHR:
case MVE_SQSHL:
case MVE_SRSHR:
case MVE_UQRSHL:
case MVE_UQSHL:
case MVE_URSHR:
case MVE_VABDf16:
case MVE_VABDf32:
case MVE_VABDs16:
case MVE_VABDs32:
case MVE_VABDs8:
case MVE_VABDu16:
case MVE_VABDu32:
case MVE_VABDu8:
case MVE_VABSf16:
case MVE_VABSf32:
case MVE_VABSs16:
case MVE_VABSs32:
case MVE_VABSs8:
case MVE_VADD_qr_f16:
case MVE_VADD_qr_f32:
case MVE_VADD_qr_i16:
case MVE_VADD_qr_i32:
case MVE_VADD_qr_i8:
case MVE_VADDVs16acc:
case MVE_VADDVs16no_acc:
case MVE_VADDVs32acc:
case MVE_VADDVs32no_acc:
case MVE_VADDVs8acc:
case MVE_VADDVs8no_acc:
case MVE_VADDVu16acc:
case MVE_VADDVu16no_acc:
case MVE_VADDVu32acc:
case MVE_VADDVu32no_acc:
case MVE_VADDVu8acc:
case MVE_VADDVu8no_acc:
case MVE_VADDf16:
case MVE_VADDf32:
case MVE_VADDi16:
case MVE_VADDi32:
case MVE_VADDi8:
case MVE_VAND:
case MVE_VBIC:
case MVE_VBICimmi16:
case MVE_VBICimmi32:
case MVE_VBRSR16:
case MVE_VBRSR32:
case MVE_VBRSR8:
case MVE_VCLSs16:
case MVE_VCLSs32:
case MVE_VCLSs8:
case MVE_VCLZs16:
case MVE_VCLZs32:
case MVE_VCLZs8:
case MVE_VCMPf16:
case MVE_VCMPf16r:
case MVE_VCMPf32:
case MVE_VCMPf32r:
case MVE_VCMPi16:
case MVE_VCMPi16r:
case MVE_VCMPi32:
case MVE_VCMPi32r:
case MVE_VCMPi8:
case MVE_VCMPi8r:
case MVE_VCMPs16:
case MVE_VCMPs16r:
case MVE_VCMPs32:
case MVE_VCMPs32r:
case MVE_VCMPs8:
case MVE_VCMPs8r:
case MVE_VCMPu16:
case MVE_VCMPu16r:
case MVE_VCMPu32:
case MVE_VCMPu32r:
case MVE_VCMPu8:
case MVE_VCMPu8r:
case MVE_VCTP16:
case MVE_VCTP32:
case MVE_VCTP64:
case MVE_VCTP8:
case MVE_VCVTf16s16_fix:
case MVE_VCVTf16s16n:
case MVE_VCVTf16u16_fix:
case MVE_VCVTf16u16n:
case MVE_VCVTf32s32_fix:
case MVE_VCVTf32s32n:
case MVE_VCVTf32u32_fix:
case MVE_VCVTf32u32n:
case MVE_VCVTs16f16_fix:
case MVE_VCVTs16f16a:
case MVE_VCVTs16f16m:
case MVE_VCVTs16f16n:
case MVE_VCVTs16f16p:
case MVE_VCVTs16f16z:
case MVE_VCVTs32f32_fix:
case MVE_VCVTs32f32a:
case MVE_VCVTs32f32m:
case MVE_VCVTs32f32n:
case MVE_VCVTs32f32p:
case MVE_VCVTs32f32z:
case MVE_VCVTu16f16_fix:
case MVE_VCVTu16f16a:
case MVE_VCVTu16f16m:
case MVE_VCVTu16f16n:
case MVE_VCVTu16f16p:
case MVE_VCVTu16f16z:
case MVE_VCVTu32f32_fix:
case MVE_VCVTu32f32a:
case MVE_VCVTu32f32m:
case MVE_VCVTu32f32n:
case MVE_VCVTu32f32p:
case MVE_VCVTu32f32z:
case MVE_VDDUPu16:
case MVE_VDDUPu32:
case MVE_VDDUPu8:
case MVE_VDUP16:
case MVE_VDUP32:
case MVE_VDUP8:
case MVE_VDWDUPu16:
case MVE_VDWDUPu32:
case MVE_VDWDUPu8:
case MVE_VEOR:
case MVE_VFMA_qr_Sf16:
case MVE_VFMA_qr_Sf32:
case MVE_VFMA_qr_f16:
case MVE_VFMA_qr_f32:
case MVE_VFMAf16:
case MVE_VFMAf32:
case MVE_VFMSf16:
case MVE_VFMSf32:
case MVE_VMAXAs16:
case MVE_VMAXAs32:
case MVE_VMAXAs8:
case MVE_VMAXs16:
case MVE_VMAXs32:
case MVE_VMAXs8:
case MVE_VMAXu16:
case MVE_VMAXu32:
case MVE_VMAXu8:
case MVE_VMINAs16:
case MVE_VMINAs32:
case MVE_VMINAs8:
case MVE_VMINs16:
case MVE_VMINs32:
case MVE_VMINs8:
case MVE_VMINu16:
case MVE_VMINu32:
case MVE_VMINu8:
case MVE_VMLADAVas16:
case MVE_VMLADAVas32:
case MVE_VMLADAVas8:
case MVE_VMLADAVau16:
case MVE_VMLADAVau32:
case MVE_VMLADAVau8:
case MVE_VMLADAVs16:
case MVE_VMLADAVs32:
case MVE_VMLADAVs8:
case MVE_VMLADAVu16:
case MVE_VMLADAVu32:
case MVE_VMLADAVu8:
case MVE_VMLALDAVs16:
case MVE_VMLALDAVs32:
case MVE_VMLALDAVu16:
case MVE_VMLALDAVu32:
case MVE_VMLALDAVas16:
case MVE_VMLALDAVas32:
case MVE_VMLALDAVau16:
case MVE_VMLALDAVau32:
case MVE_VMLSDAVas16:
case MVE_VMLSDAVas32:
case MVE_VMLSDAVas8:
case MVE_VMLSDAVs16:
case MVE_VMLSDAVs32:
case MVE_VMLSDAVs8:
case MVE_VMLSLDAVas16:
case MVE_VMLSLDAVas32:
case MVE_VMLSLDAVs16:
case MVE_VMLSLDAVs32:
case MVE_VRMLALDAVHas32:
case MVE_VRMLALDAVHau32:
case MVE_VRMLALDAVHs32:
case MVE_VRMLALDAVHu32:
case MVE_VRMLSLDAVHas32:
case MVE_VRMLSLDAVHs32:
case MVE_VMLAS_qr_s16:
case MVE_VMLAS_qr_s32:
case MVE_VMLAS_qr_s8:
case MVE_VMLAS_qr_u16:
case MVE_VMLAS_qr_u32:
case MVE_VMLAS_qr_u8:
case MVE_VMLA_qr_s16:
case MVE_VMLA_qr_s32:
case MVE_VMLA_qr_s8:
case MVE_VMLA_qr_u16:
case MVE_VMLA_qr_u32:
case MVE_VMLA_qr_u8:
case MVE_VHADD_qr_s16:
case MVE_VHADD_qr_s32:
case MVE_VHADD_qr_s8:
case MVE_VHADD_qr_u16:
case MVE_VHADD_qr_u32:
case MVE_VHADD_qr_u8:
case MVE_VHADDs16:
case MVE_VHADDs32:
case MVE_VHADDs8:
case MVE_VHADDu16:
case MVE_VHADDu32:
case MVE_VHADDu8:
case MVE_VHSUB_qr_s16:
case MVE_VHSUB_qr_s32:
case MVE_VHSUB_qr_s8:
case MVE_VHSUB_qr_u16:
case MVE_VHSUB_qr_u32:
case MVE_VHSUB_qr_u8:
case MVE_VHSUBs16:
case MVE_VHSUBs32:
case MVE_VHSUBs8:
case MVE_VHSUBu16:
case MVE_VHSUBu32:
case MVE_VHSUBu8:
case MVE_VIDUPu16:
case MVE_VIDUPu32:
case MVE_VIDUPu8:
case MVE_VIWDUPu16:
case MVE_VIWDUPu32:
case MVE_VIWDUPu8:
case MVE_VLDRBS16:
case MVE_VLDRBS16_post:
case MVE_VLDRBS16_pre:
case MVE_VLDRBS16_rq:
case MVE_VLDRBS32:
case MVE_VLDRBS32_post:
case MVE_VLDRBS32_pre:
case MVE_VLDRBS32_rq:
case MVE_VLDRBU16:
case MVE_VLDRBU16_post:
case MVE_VLDRBU16_pre:
case MVE_VLDRBU16_rq:
case MVE_VLDRBU32:
case MVE_VLDRBU32_post:
case MVE_VLDRBU32_pre:
case MVE_VLDRBU32_rq:
case MVE_VLDRBU8:
case MVE_VLDRBU8_post:
case MVE_VLDRBU8_pre:
case MVE_VLDRBU8_rq:
case MVE_VLDRDU64_qi:
case MVE_VLDRDU64_qi_pre:
case MVE_VLDRDU64_rq:
case MVE_VLDRDU64_rq_u:
case MVE_VLDRHS32:
case MVE_VLDRHS32_post:
case MVE_VLDRHS32_pre:
case MVE_VLDRHS32_rq:
case MVE_VLDRHS32_rq_u:
case MVE_VLDRHU16:
case MVE_VLDRHU16_post:
case MVE_VLDRHU16_pre:
case MVE_VLDRHU16_rq:
case MVE_VLDRHU16_rq_u:
case MVE_VLDRHU32:
case MVE_VLDRHU32_post:
case MVE_VLDRHU32_pre:
case MVE_VLDRHU32_rq:
case MVE_VLDRHU32_rq_u:
case MVE_VLDRWU32:
case MVE_VLDRWU32_post:
case MVE_VLDRWU32_pre:
case MVE_VLDRWU32_qi:
case MVE_VLDRWU32_qi_pre:
case MVE_VLDRWU32_rq:
case MVE_VLDRWU32_rq_u:
case MVE_VMOVimmf32:
case MVE_VMOVimmi16:
case MVE_VMOVimmi32:
case MVE_VMOVimmi64:
case MVE_VMOVimmi8:
case MVE_VMOVNi16bh:
case MVE_VMOVNi16th:
case MVE_VMOVNi32bh:
case MVE_VMOVNi32th:
case MVE_VMULLBp16:
case MVE_VMULLBp8:
case MVE_VMULLBs16:
case MVE_VMULLBs32:
case MVE_VMULLBs8:
case MVE_VMULLBu16:
case MVE_VMULLBu32:
case MVE_VMULLBu8:
case MVE_VMULLTp16:
case MVE_VMULLTp8:
case MVE_VMULLTs16:
case MVE_VMULLTs32:
case MVE_VMULLTs8:
case MVE_VMULLTu16:
case MVE_VMULLTu32:
case MVE_VMULLTu8:
case MVE_VMUL_qr_f16:
case MVE_VMUL_qr_f32:
case MVE_VMUL_qr_i16:
case MVE_VMUL_qr_i32:
case MVE_VMUL_qr_i8:
case MVE_VMULf16:
case MVE_VMULf32:
case MVE_VMULi16:
case MVE_VMULi8:
case MVE_VMULi32:
case MVE_VMVN:
case MVE_VMVNimmi16:
case MVE_VMVNimmi32:
case MVE_VNEGf16:
case MVE_VNEGf32:
case MVE_VNEGs16:
case MVE_VNEGs32:
case MVE_VNEGs8:
case MVE_VORN:
case MVE_VORR:
case MVE_VORRimmi16:
case MVE_VORRimmi32:
case MVE_VPST:
case MVE_VQABSs16:
case MVE_VQABSs32:
case MVE_VQABSs8:
case MVE_VQADD_qr_s16:
case MVE_VQADD_qr_s32:
case MVE_VQADD_qr_s8:
case MVE_VQADD_qr_u16:
case MVE_VQADD_qr_u32:
case MVE_VQADD_qr_u8:
case MVE_VQADDs16:
case MVE_VQADDs32:
case MVE_VQADDs8:
case MVE_VQADDu16:
case MVE_VQADDu32:
case MVE_VQADDu8:
case MVE_VQDMULL_qr_s16bh:
case MVE_VQDMULL_qr_s16th:
case MVE_VQDMULL_qr_s32bh:
case MVE_VQDMULL_qr_s32th:
case MVE_VQDMULLs16bh:
case MVE_VQDMULLs16th:
case MVE_VQDMULLs32bh:
case MVE_VQDMULLs32th:
case MVE_VQNEGs16:
case MVE_VQNEGs32:
case MVE_VQNEGs8:
case MVE_VQMOVNs16bh:
case MVE_VQMOVNs16th:
case MVE_VQMOVNs32bh:
case MVE_VQMOVNs32th:
case MVE_VQMOVNu16bh:
case MVE_VQMOVNu16th:
case MVE_VQMOVNu32bh:
case MVE_VQMOVNu32th:
case MVE_VQMOVUNs16bh:
case MVE_VQMOVUNs16th:
case MVE_VQMOVUNs32bh:
case MVE_VQMOVUNs32th:
case MVE_VQRSHL_by_vecs16:
case MVE_VQRSHL_by_vecs32:
case MVE_VQRSHL_by_vecs8:
case MVE_VQRSHL_by_vecu16:
case MVE_VQRSHL_by_vecu32:
case MVE_VQRSHL_by_vecu8:
case MVE_VQRSHL_qrs16:
case MVE_VQRSHL_qrs32:
case MVE_VQRSHL_qrs8:
case MVE_VQRSHL_qru16:
case MVE_VQRSHL_qru8:
case MVE_VQRSHL_qru32:
case MVE_VQSHLU_imms16:
case MVE_VQSHLU_imms32:
case MVE_VQSHLU_imms8:
case MVE_VQSHLimms16:
case MVE_VQSHLimms32:
case MVE_VQSHLimms8:
case MVE_VQSHLimmu16:
case MVE_VQSHLimmu32:
case MVE_VQSHLimmu8:
case MVE_VQSHL_by_vecs16:
case MVE_VQSHL_by_vecs32:
case MVE_VQSHL_by_vecs8:
case MVE_VQSHL_by_vecu16:
case MVE_VQSHL_by_vecu32:
case MVE_VQSHL_by_vecu8:
case MVE_VQSHL_qrs16:
case MVE_VQSHL_qrs32:
case MVE_VQSHL_qrs8:
case MVE_VQSHL_qru16:
case MVE_VQSHL_qru32:
case MVE_VQSHL_qru8:
case MVE_VQRSHRNbhs16:
case MVE_VQRSHRNbhs32:
case MVE_VQRSHRNbhu16:
case MVE_VQRSHRNbhu32:
case MVE_VQRSHRNths16:
case MVE_VQRSHRNths32:
case MVE_VQRSHRNthu16:
case MVE_VQRSHRNthu32:
case MVE_VQRSHRUNs16bh:
case MVE_VQRSHRUNs16th:
case MVE_VQRSHRUNs32bh:
case MVE_VQRSHRUNs32th:
case MVE_VQSHRNbhs16:
case MVE_VQSHRNbhs32:
case MVE_VQSHRNbhu16:
case MVE_VQSHRNbhu32:
case MVE_VQSHRNths16:
case MVE_VQSHRNths32:
case MVE_VQSHRNthu16:
case MVE_VQSHRNthu32:
case MVE_VQSHRUNs16bh:
case MVE_VQSHRUNs16th:
case MVE_VQSHRUNs32bh:
case MVE_VQSHRUNs32th:
case MVE_VQSUB_qr_s16:
case MVE_VQSUB_qr_s32:
case MVE_VQSUB_qr_s8:
case MVE_VQSUB_qr_u16:
case MVE_VQSUB_qr_u32:
case MVE_VQSUB_qr_u8:
case MVE_VQSUBs16:
case MVE_VQSUBs32:
case MVE_VQSUBs8:
case MVE_VQSUBu16:
case MVE_VQSUBu32:
case MVE_VQSUBu8:
case MVE_VRHADDs16:
case MVE_VRHADDs32:
case MVE_VRHADDs8:
case MVE_VRHADDu16:
case MVE_VRHADDu32:
case MVE_VRHADDu8:
case MVE_VRINTf16A:
case MVE_VRINTf16M:
case MVE_VRINTf16N:
case MVE_VRINTf16P:
case MVE_VRINTf16X:
case MVE_VRINTf16Z:
case MVE_VRINTf32A:
case MVE_VRINTf32M:
case MVE_VRINTf32N:
case MVE_VRINTf32P:
case MVE_VRINTf32X:
case MVE_VRINTf32Z:
case MVE_VRSHL_by_vecs16:
case MVE_VRSHL_by_vecs32:
case MVE_VRSHL_by_vecs8:
case MVE_VRSHL_by_vecu16:
case MVE_VRSHL_by_vecu32:
case MVE_VRSHL_by_vecu8:
case MVE_VRSHL_qrs16:
case MVE_VRSHL_qrs32:
case MVE_VRSHL_qrs8:
case MVE_VRSHL_qru16:
case MVE_VRSHL_qru32:
case MVE_VRSHL_qru8:
case MVE_VRSHR_imms16:
case MVE_VRSHR_imms32:
case MVE_VRSHR_imms8:
case MVE_VRSHR_immu16:
case MVE_VRSHR_immu32:
case MVE_VRSHR_immu8:
case MVE_VRSHRNi16bh:
case MVE_VRSHRNi16th:
case MVE_VRSHRNi32bh:
case MVE_VRSHRNi32th:
case MVE_VSHL_by_vecs16:
case MVE_VSHL_by_vecs32:
case MVE_VSHL_by_vecs8:
case MVE_VSHL_by_vecu16:
case MVE_VSHL_by_vecu32:
case MVE_VSHL_by_vecu8:
case MVE_VSHL_immi16:
case MVE_VSHL_immi32:
case MVE_VSHL_immi8:
case MVE_VSHL_qrs16:
case MVE_VSHL_qrs32:
case MVE_VSHL_qrs8:
case MVE_VSHL_qru16:
case MVE_VSHL_qru32:
case MVE_VSHL_qru8:
case MVE_VSHR_imms16:
case MVE_VSHR_imms32:
case MVE_VSHR_imms8:
case MVE_VSHR_immu16:
case MVE_VSHR_immu32:
case MVE_VSHR_immu8:
case MVE_VSHRNi16bh:
case MVE_VSHRNi16th:
case MVE_VSHRNi32bh:
case MVE_VSHRNi32th:
case MVE_VSLIimm16:
case MVE_VSLIimm32:
case MVE_VSLIimm8:
case MVE_VSRIimm16:
case MVE_VSRIimm32:
case MVE_VSRIimm8:
case MVE_VSTRB16:
case MVE_VSTRB16_post:
case MVE_VSTRB16_pre:
case MVE_VSTRB16_rq:
case MVE_VSTRB32:
case MVE_VSTRB32_post:
case MVE_VSTRB32_pre:
case MVE_VSTRB32_rq:
case MVE_VSTRB8_rq:
case MVE_VSTRBU8:
case MVE_VSTRBU8_post:
case MVE_VSTRBU8_pre:
case MVE_VSTRD64_qi:
case MVE_VSTRD64_qi_pre:
case MVE_VSTRD64_rq:
case MVE_VSTRD64_rq_u:
case MVE_VSTRH16_rq:
case MVE_VSTRH16_rq_u:
case MVE_VSTRH32:
case MVE_VSTRH32_post:
case MVE_VSTRH32_pre:
case MVE_VSTRH32_rq:
case MVE_VSTRH32_rq_u:
case MVE_VSTRHU16:
case MVE_VSTRHU16_post:
case MVE_VSTRHU16_pre:
case MVE_VSTRW32_qi:
case MVE_VSTRW32_qi_pre:
case MVE_VSTRW32_rq:
case MVE_VSTRW32_rq_u:
case MVE_VSTRWU32:
case MVE_VSTRWU32_post:
case MVE_VSTRWU32_pre:
case MVE_VSUB_qr_f16:
case MVE_VSUB_qr_f32:
case MVE_VSUB_qr_i16:
case MVE_VSUB_qr_i32:
case MVE_VSUB_qr_i8:
case MVE_VSUBf16:
case MVE_VSUBf32:
case MVE_VSUBi16:
case MVE_VSUBi32:
case MVE_VSUBi8:
return true;
}
};
LLVMInitializeARMTargetInfo();
LLVMInitializeARMTarget();
LLVMInitializeARMTargetMC();
auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
std::string Error;
const Target *T = TargetRegistry::lookupTarget(TT, Error);
if (!T) {
dbgs() << Error;
return;
}
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine*>(
T->createTargetMachine(TT, "generic", "", Options, None, None,
CodeGenOpt::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
const ARMBaseInstrInfo *TII = ST.getInstrInfo();
auto MII = TM->getMCInstrInfo();
for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
const MCInstrDesc &Desc = TII->get(i);
for (auto &Op : Desc.operands()) {
// Only check instructions that access the MQPR regs.
if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
Op.RegClass != ARM::MQPRRegClassID)
continue;
uint64_t Flags = MII->get(i).TSFlags;
bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
ASSERT_EQ(IsValidTPOpcode(i), Valid)
<< MII->getName(i)
<< ": mismatched expectation for tail-predicated safety\n";
break;
}
}
}
TEST(MachineInstr, HasSideEffects) {
using namespace ARM;
std::set<unsigned> UnpredictableOpcodes = {
// MVE Instructions
MVE_VCTP8,
MVE_VCTP16,
MVE_VCTP32,
MVE_VCTP64,
MVE_VPST,
MVE_VPTv16i8,
MVE_VPTv8i16,
MVE_VPTv4i32,
MVE_VPTv16i8r,
MVE_VPTv8i16r,
MVE_VPTv4i32r,
MVE_VPTv16s8,
MVE_VPTv8s16,
MVE_VPTv4s32,
MVE_VPTv16s8r,
MVE_VPTv8s16r,
MVE_VPTv4s32r,
MVE_VPTv16u8,
MVE_VPTv8u16,
MVE_VPTv4u32,
MVE_VPTv16u8r,
MVE_VPTv8u16r,
MVE_VPTv4u32r,
MVE_VPTv8f16,
MVE_VPTv4f32,
MVE_VPTv8f16r,
MVE_VPTv4f32r,
MVE_VADC,
MVE_VADCI,
MVE_VSBC,
MVE_VSBCI,
MVE_VSHLC,
// FP Instructions
FLDMXIA,
FLDMXDB_UPD,
FLDMXIA_UPD,
FSTMXDB_UPD,
FSTMXIA,
FSTMXIA_UPD,
VLDR_FPCXTNS_off,
VLDR_FPCXTNS_off,
VLDR_FPCXTNS_post,
VLDR_FPCXTNS_pre,
VLDR_FPCXTS_off,
VLDR_FPCXTS_post,
VLDR_FPCXTS_pre,
VLDR_FPSCR_NZCVQC_off,
VLDR_FPSCR_NZCVQC_post,
VLDR_FPSCR_NZCVQC_pre,
VLDR_FPSCR_off,
VLDR_FPSCR_post,
VLDR_FPSCR_pre,
VLDR_P0_off,
VLDR_P0_post,
VLDR_P0_pre,
VLDR_VPR_off,
VLDR_VPR_post,
VLDR_VPR_pre,
VLLDM,
VLSTM,
VMRS,
VMRS_FPCXTNS,
VMRS_FPCXTS,
VMRS_FPEXC,
VMRS_FPINST,
VMRS_FPINST2,
VMRS_FPSCR_NZCVQC,
VMRS_FPSID,
VMRS_MVFR0,
VMRS_MVFR1,
VMRS_MVFR2,
VMRS_P0,
VMRS_VPR,
VMSR,
VMSR_FPCXTNS,
VMSR_FPCXTS,
VMSR_FPEXC,
VMSR_FPINST,
VMSR_FPINST2,
VMSR_FPSCR_NZCVQC,
VMSR_FPSID,
VMSR_P0,
VMSR_VPR,
VSCCLRMD,
VSCCLRMS,
VSTR_FPCXTNS_off,
VSTR_FPCXTNS_post,
VSTR_FPCXTNS_pre,
VSTR_FPCXTS_off,
VSTR_FPCXTS_post,
VSTR_FPCXTS_pre,
VSTR_FPSCR_NZCVQC_off,
VSTR_FPSCR_NZCVQC_post,
VSTR_FPSCR_NZCVQC_pre,
VSTR_FPSCR_off,
VSTR_FPSCR_post,
VSTR_FPSCR_pre,
VSTR_P0_off,
VSTR_P0_post,
VSTR_P0_pre,
VSTR_VPR_off,
VSTR_VPR_post,
VSTR_VPR_pre,
};
LLVMInitializeARMTargetInfo();
LLVMInitializeARMTarget();
LLVMInitializeARMTargetMC();
auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
std::string Error;
const Target *T = TargetRegistry::lookupTarget(TT, Error);
if (!T) {
dbgs() << Error;
return;
}
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(
static_cast<LLVMTargetMachine *>(T->createTargetMachine(
TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
const ARMBaseInstrInfo *TII = ST.getInstrInfo();
auto MII = TM->getMCInstrInfo();
for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {
const MCInstrDesc &Desc = TII->get(Op);
if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE &&
(Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainVFP)
continue;
if (UnpredictableOpcodes.count(Op))
continue;
ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
<< MII->getName(Op) << " has unexpected side effects";
}
}