peephole-fold-testrr.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt -mtriple=x86_64-- %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define i32 @atomic(i8** %arg) {
%load = load atomic i8*, i8** %arg unordered, align 8
%cmp = icmp eq i8* %load, null
%zext = zext i1 %cmp to i32
ret i32 %zext
}
define i32 @nonatomic_unoptimized(i8** %arg) {
%load = load i8*, i8** %arg, align 8
%cmp = icmp eq i8* %load, null
%zext = zext i1 %cmp to i32
ret i32 %zext
}
...
---
name: atomic
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr64 }
- { id: 2, class: gr8 }
- { id: 3, class: gr32 }
liveins:
- { reg: '$rdi', virtual-reg: '%0' }
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi
; CHECK-LABEL: name: atomic
; CHECK: liveins: $rdi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: CMP64mi8 [[COPY]], 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load unordered 8 from %ir.arg)
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
; CHECK: $eax = COPY [[MOVZX32rr8_]]
; CHECK: RET 0, $eax
%0:gr64 = COPY $rdi
%1:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load unordered 8 from %ir.arg)
TEST64rr %1, %1, implicit-def $eflags
%2:gr8 = SETCCr 4, implicit $eflags
%3:gr32 = MOVZX32rr8 killed %2
$eax = COPY %3
RET 0, $eax
...
---
name: nonatomic_unoptimized
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr64 }
- { id: 2, class: gr8 }
- { id: 3, class: gr32 }
liveins:
- { reg: '$rdi', virtual-reg: '%0' }
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi
; CHECK-LABEL: name: nonatomic_unoptimized
; CHECK: liveins: $rdi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: CMP64mi8 [[COPY]], 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 8 from %ir.arg)
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
; CHECK: $eax = COPY [[MOVZX32rr8_]]
; CHECK: RET 0, $eax
%0:gr64 = COPY $rdi
%1:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load 8 from %ir.arg)
TEST64rr %1, %1, implicit-def $eflags
%2:gr8 = SETCCr 4, implicit $eflags
%3:gr32 = MOVZX32rr8 killed %2
$eax = COPY %3
RET 0, $eax
...