llvm.amdgcn.interp.p1.f16.ll
5.09 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-32BANK %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-32BANK %s
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-16BANK %s
define amdgpu_ps float @interp_f16(float %i, i32 inreg %m0) #0 {
; GFX9-32BANK-LABEL: interp_f16:
; GFX9-32BANK: ; %bb.0:
; GFX9-32BANK-NEXT: s_mov_b32 m0, s0
; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
; GFX9-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-32BANK-LABEL: interp_f16:
; GFX8-32BANK: ; %bb.0:
; GFX8-32BANK-NEXT: s_mov_b32 m0, s0
; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
; GFX8-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-16BANK-LABEL: interp_f16:
; GFX8-16BANK: ; %bb.0:
; GFX8-16BANK-NEXT: s_mov_b32 m0, s0
; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y
; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1
; GFX8-16BANK-NEXT: ; return to shader part epilog
%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0)
ret float %res
}
define amdgpu_ps float @interp_f16_high(float %i, i32 inreg %m0) #0 {
; GFX9-32BANK-LABEL: interp_f16_high:
; GFX9-32BANK: ; %bb.0:
; GFX9-32BANK-NEXT: s_mov_b32 m0, s0
; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high
; GFX9-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-32BANK-LABEL: interp_f16_high:
; GFX8-32BANK: ; %bb.0:
; GFX8-32BANK-NEXT: s_mov_b32 m0, s0
; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high
; GFX8-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-16BANK-LABEL: interp_f16_high:
; GFX8-16BANK: ; %bb.0:
; GFX8-16BANK-NEXT: s_mov_b32 m0, s0
; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y
; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1 high
; GFX8-16BANK-NEXT: ; return to shader part epilog
%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 true, i32 %m0)
ret float %res
}
define amdgpu_ps float @interp_f16_0_0(float %i, i32 inreg %m0) #0 {
; GFX9-32BANK-LABEL: interp_f16_0_0:
; GFX9-32BANK: ; %bb.0:
; GFX9-32BANK-NEXT: s_mov_b32 m0, s0
; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x
; GFX9-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-32BANK-LABEL: interp_f16_0_0:
; GFX8-32BANK: ; %bb.0:
; GFX8-32BANK-NEXT: s_mov_b32 m0, s0
; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x
; GFX8-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-16BANK-LABEL: interp_f16_0_0:
; GFX8-16BANK: ; %bb.0:
; GFX8-16BANK-NEXT: s_mov_b32 m0, s0
; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr0.x
; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr0.x, v1
; GFX8-16BANK-NEXT: ; return to shader part epilog
%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 0, i32 0, i1 false, i32 %m0)
ret float %res
}
; Copy needed to legalize %i
define amdgpu_ps float @interp_f16_sgpr_i(float inreg %i,i32 inreg %m0) #0 {
; GFX9-32BANK-LABEL: interp_f16_sgpr_i:
; GFX9-32BANK: ; %bb.0:
; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
; GFX9-32BANK-NEXT: s_mov_b32 m0, s1
; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
; GFX9-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-32BANK-LABEL: interp_f16_sgpr_i:
; GFX8-32BANK: ; %bb.0:
; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
; GFX8-32BANK-NEXT: s_mov_b32 m0, s1
; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
; GFX8-32BANK-NEXT: ; return to shader part epilog
;
; GFX8-16BANK-LABEL: interp_f16_sgpr_i:
; GFX8-16BANK: ; %bb.0:
; GFX8-16BANK-NEXT: s_mov_b32 m0, s1
; GFX8-16BANK-NEXT: v_mov_b32_e32 v0, s0
; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y
; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1
; GFX8-16BANK-NEXT: ; return to shader part epilog
%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0)
ret float %res
}
declare float @llvm.amdgcn.interp.p1.f16(float, i32 immarg, i32 immarg, i1 immarg, i32) #0
attributes #0 = { nounwind readnone speculatable }