region_multiexit_partialwrite___%bb3---%bb19.jscop
1.4 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
{
"arrays": [
{
"name": "MemRef_arg",
"sizes": [
"*"
],
"type": "i32"
},
{
"name": "MemRef_arg2",
"sizes": [
"*"
],
"type": "i32"
}
],
"context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
"name": "%bb3---%bb19",
"statements": [
{
"accesses": [
{
"kind": "read",
"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
},
{
"kind": "write",
"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_tmp11__phi[] }"
}
],
"domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
"name": "Stmt_bb3__TO__bb10",
"schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
},
{
"accesses": [
{
"kind": "read",
"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_tmp11__phi[] }"
},
{
"kind": "write",
"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
}
],
"domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
"name": "Stmt_bb10",
"schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
}
]
}