ExtendedAtomicOps-x86-64.h
8.63 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
#if defined(_MSC_VER)
# include "os/Win32/WindowsHeaders.h"
# include <intrin.h>
#endif
#if defined(__SSE2__)
# include <emmintrin.h>
#endif
static inline void atomic_thread_fence(memory_order_relaxed_t)
{
}
static inline void atomic_thread_fence(memory_order_release_t)
{
#if defined(_MSC_VER)
_ReadWriteBarrier();
#else
__asm__ __volatile__ ("" : : : "memory");
#endif
}
static inline void atomic_thread_fence(memory_order_acquire_t)
{
#if defined(_MSC_VER)
_ReadWriteBarrier();
#else
__asm__ __volatile__ ("" : : : "memory");
#endif
}
static inline void atomic_thread_fence(memory_order_acq_rel_t)
{
#if defined(_MSC_VER)
_ReadWriteBarrier();
#else
__asm__ __volatile__ ("" : : : "memory");
#endif
}
static inline void atomic_thread_fence(int /* memory_order_seq_cst_t */)
{
#if defined(__SSE2__)
_mm_mfence();
#elif defined(_MSC_VER)
volatile LONGLONG tmp;
_InterlockedOr64(&tmp, 0);
#else
__asm__ __volatile__ ("lock orl #0, 0(%%esp)" ::: "cc", "memory");
#endif
}
/*
* int support
*/
static inline int atomic_load_explicit(const volatile int* p, memory_order_relaxed_t)
{
return *p;
}
static inline int atomic_load_explicit(const volatile int* p, int)
{
int v;
#if defined(_MSC_VER)
v = *p;
_ReadWriteBarrier();
#else
__asm__ __volatile__ ("movl %1, %0" : "=r" (v) : "m" (*p) : "memory");
#endif
return v;
}
static inline void atomic_store_explicit(volatile int* p, int v, memory_order_relaxed_t)
{
*p = v;
}
static inline void atomic_store_explicit(volatile int* p, int v, memory_order_release_t)
{
#if defined(_MSC_VER)
_ReadWriteBarrier();
*p = v;
#else
__asm__ __volatile__ ("movl %1, %0" : "=m" (*p) : "r" (v) : "memory");
#endif
}
static inline void atomic_store_explicit(volatile int* p, int val, int /* memory_order_seq_cst_t */)
{
#if defined(_MSC_VER)
_InterlockedExchange((volatile LONG*)p, (LONG)val);
#else
// lock prefix is implicit
__asm__ __volatile__
(
/*lock*/ "xchgl %1, %0"
: "+m" (*p), "+r" (val)
:
: "memory"
);
#endif
}
static inline int atomic_exchange_explicit(volatile int* p, int val, int)
{
#if defined(_MSC_VER)
return (int)_InterlockedExchange((volatile long*)p, (long)val);
#else
// lock prefix is implicit
__asm__ __volatile__
(
/*lock*/ "xchg %1, %0"
: "+m" (*p), "+r" (val)
:
: "memory"
);
return val;
#endif
}
static inline bool atomic_compare_exchange_strong_explicit(volatile int* p, int* oldval, int newval, int, int)
{
#if defined(_MSC_VER)
int tmp = (int)_InterlockedCompareExchange((volatile long*)p, (long)newval, (long)*oldval);
return *oldval == tmp ? true : (*oldval = tmp, false);
#else
char res;
__asm__ __volatile__
(
"lock cmpxchg %3, %0\n\t"
"setz %b1"
: "+m" (*p), "=q" (res), "+a" (*oldval)
: "r" (newval)
: "cc", "memory"
);
return res != 0;
#endif
}
static inline bool atomic_compare_exchange_weak_explicit(volatile int* p, int* oldval, int newval, int, int)
{
return atomic_compare_exchange_strong_explicit(p, oldval, newval, memory_order_seq_cst, memory_order_seq_cst);
}
/*
* native word support
*/
static inline atomic_word atomic_load_explicit(const volatile atomic_word* p, memory_order_relaxed_t)
{
return *p;
}
static inline atomic_word atomic_load_explicit(const volatile atomic_word* p, int)
{
atomic_word v;
#if defined(_MSC_VER)
v = *p;
_ReadWriteBarrier();
#else
__asm__ __volatile__ ("movq %1, %0" : "=r" (v) : "m" (*p) : "memory");
#endif
return v;
}
static inline void atomic_store_explicit(volatile atomic_word* p, atomic_word v, memory_order_relaxed_t)
{
*p = v;
}
static inline void atomic_store_explicit(volatile atomic_word* p, atomic_word v, memory_order_release_t)
{
#if defined(_MSC_VER)
_ReadWriteBarrier();
*p = v;
#else
__asm__ __volatile__ ("movq %1, %0" : "=m" (*p) : "r" (v) : "memory");
#endif
}
static inline void atomic_store_explicit(volatile atomic_word* p, atomic_word val, int /* memory_order_seq_cst_t */)
{
#if defined(_MSC_VER)
_InterlockedExchange64((volatile LONGLONG*)p, (LONGLONG)val);
#else
// lock prefix is implicit
__asm__ __volatile__
(
/*lock*/ "xchgq %1, %0"
: "+m" (*p), "+r" (val)
:
: "memory"
);
#endif
}
static inline atomic_word atomic_exchange_explicit(volatile atomic_word* p, atomic_word val, int)
{
#if defined(_MSC_VER)
return (atomic_word)_InterlockedExchange64((volatile LONGLONG*)p, (LONGLONG)val);
#else
// lock prefix is implicit
__asm__ __volatile__
(
/*lock*/ "xchgq %1, %0"
: "+m" (*p), "+r" (val)
:
: "memory"
);
return val;
#endif
}
static inline bool atomic_compare_exchange_strong_explicit(volatile atomic_word* p, atomic_word* oldval, atomic_word newval, int, int)
{
#if defined(_MSC_VER)
atomic_word tmp = (atomic_word)_InterlockedCompareExchange64((volatile LONGLONG*)p, (LONGLONG)newval, (LONGLONG)*oldval);
return *oldval == tmp ? true : (*oldval = tmp, false);
#else
char res;
__asm__ __volatile__
(
"lock cmpxchgq %3, %0\n\t"
"setz %b1"
: "+m" (*p), "=q" (res), "+a" (*oldval)
: "r" (newval)
: "cc", "memory"
);
return res != 0;
#endif
}
static inline bool atomic_compare_exchange_weak_explicit(volatile atomic_word* p, atomic_word* oldval, atomic_word newval, int, int)
{
return atomic_compare_exchange_strong_explicit(p, oldval, newval, memory_order_seq_cst, memory_order_seq_cst);
}
static inline atomic_word atomic_fetch_add_explicit(volatile int *p, int val, int)
{
#if defined(_MSC_VER)
return _InterlockedExchangeAdd((LONG volatile*)p, (LONG)val);
#else
__asm__ __volatile__
(
"lock xaddl\t%1, %0"
: "+m" (*p), "+r" (val)
:
: "cc", "memory"
);
return val;
#endif
}
static inline atomic_word atomic_fetch_add_explicit(volatile atomic_word *p, atomic_word val, int)
{
#if defined(_MSC_VER)
return _InterlockedExchangeAdd64((LONGLONG volatile*)p, (LONGLONG)val);
#else
__asm__ __volatile__
(
"lock xaddq %1, %0"
: "+m" (*p), "+r" (val)
:
: "cc", "memory"
);
return val;
#endif
}
static inline atomic_word atomic_fetch_sub_explicit(volatile int *p, int val, int mo)
{
return atomic_fetch_add_explicit(p, -val, mo);
}
static inline atomic_word atomic_fetch_sub_explicit(volatile atomic_word *p, atomic_word val, int mo)
{
return atomic_fetch_add_explicit(p, -val, mo);
}
/*
* extensions
*/
static inline void atomic_retain(volatile int *p)
{
#if defined(_MSC_VER)
_InterlockedIncrement((LONG volatile*)p);
#else
__asm__ (
"lock incl %0\n\t"
: "+m" (*p)
:
: "cc", "memory"
);
#endif
}
static inline bool atomic_release(volatile int *p)
{
#if defined(_MSC_VER)
return _InterlockedDecrement((LONG volatile*)p) == 0;
#else
bool res;
__asm__ (
"lock decl %0\n\t"
"setz %b1"
: "+m" (*p), "=q" (res)
:
: "cc", "memory"
);
return res;
#endif
}
/*
* double word
*/
static inline bool atomic_compare_exchange_strong_explicit(volatile atomic_word2* p, atomic_word2* oldval, atomic_word2 newval, int, int)
{
#if defined(_MSC_VER)
return _InterlockedCompareExchange128((volatile LONGLONG*)p, (LONGLONG)newval.hi, (LONGLONG)newval.lo, (LONGLONG*)oldval) != 0;
#else
char res;
__asm__ __volatile__
(
"lock cmpxchg16b %0\n\t"
"setz %b1\n\t"
: "+m" (*p), "=q" (res), "+a" (oldval->lo), "+d" (oldval->hi)
: "b" (newval.lo), "c" (newval.hi)
: "cc", "memory"
);
return res != 0;
#endif
}
static inline bool atomic_compare_exchange_weak_explicit(volatile atomic_word2* p, atomic_word2* oldval, atomic_word2 newval, int o1, int o2)
{
return atomic_compare_exchange_strong_explicit(p, oldval, newval, o1, o2);
}
static inline atomic_word2 atomic_load_explicit(const volatile atomic_word2* p, int o)
{
atomic_word2 r = { 0, 0};
atomic_word2 c = { 0, 0};
atomic_compare_exchange_strong_explicit((volatile atomic_word2*)p, &r, c, o, o);
return r;
}
static inline void atomic_store_explicit(volatile atomic_word2* p, atomic_word2 v, int o)
{
atomic_word2 c = v;
while (!atomic_compare_exchange_strong_explicit(p, &c, v, o, o))
{
}
}
static inline atomic_word2 atomic_exchange_explicit(volatile atomic_word2* p, atomic_word2 newval, int)
{
atomic_word2 oldval;
oldval.lo = 0;
oldval.hi = newval.hi - 1;
while (!atomic_compare_exchange_strong_explicit(p, &oldval, newval, memory_order_seq_cst, memory_order_seq_cst))
;
return oldval;
}