2020-1-capstone-design1 / KNW_Project2

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이재하
7d2ba55a 1 parent 71ca7fe4

Single Cycle 누락된 파일 추가

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module Mux5bit(input1, input2, signal, output1);
input[4:0] input1, input2;
input signal;
output reg[4:0] output1;
always @(*) begin
case(signal)
1'b0: output1 = input1;
1'b1: output1 = input2;
endcase
end
endmodule
module Mux32bit(input1, input2, signal, output1);
input[31:0] input1, input2;
input signal;
output reg[31:0] output1;
always @(*) begin
case(signal)
1'b0: output1 = input1;
1'b1: output1 = input2;
endcase
end
endmodule