module Mux5bit(input1, input2, signal, output1);

input[4:0] input1, input2;
input signal;
output reg[4:0] output1;

always @(*) begin
	case(signal)
		1'b0: output1 = input1;
		1'b1: output1 = input2;
	endcase
end

endmodule

module Mux32bit(input1, input2, signal, output1);

input[31:0] input1, input2;
input signal;
output reg[31:0] output1;

always @(*) begin
	case(signal)
		1'b0: output1 = input1;
		1'b1: output1 = input2;
	endcase
end

endmodule