2020-1-capstone-design1 / KNW_Project2

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Hazard 관리 기능 수정, Forwarding 방식 추가 및 오류 수정

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Showing 16 changed files with 664 additions and 337 deletions
...@@ -38,7 +38,7 @@ always @(*) begin ...@@ -38,7 +38,7 @@ always @(*) begin
38 6'b001000: begin // jr 38 6'b001000: begin // jr
39 // regdst = 1'bz; 39 // regdst = 1'bz;
40 regwrite = 1'b0; 40 regwrite = 1'b0;
41 - // alusrc = 1'bz; 41 + alusrc = 1'b1;
42 aluctrl = 4'b1111; 42 aluctrl = 4'b1111;
43 // memread = 1'b0; 43 // memread = 1'b0;
44 // memwrite = 1'b0; 44 // memwrite = 1'b0;
...@@ -51,7 +51,7 @@ always @(*) begin ...@@ -51,7 +51,7 @@ always @(*) begin
51 default: begin 51 default: begin
52 // regdst = 1'bz; 52 // regdst = 1'bz;
53 regwrite = 1'b0; 53 regwrite = 1'b0;
54 - // alusrc = 1'bz; 54 + alusrc = 1'b1;
55 aluctrl = 4'b1111; 55 aluctrl = 4'b1111;
56 // memread = 1'b0; 56 // memread = 1'b0;
57 // memwrite = 1'b0; 57 // memwrite = 1'b0;
...@@ -222,7 +222,7 @@ always @(*) begin ...@@ -222,7 +222,7 @@ always @(*) begin
222 6'b000010: begin // jump instruction 222 6'b000010: begin // jump instruction
223 // regdst = 1'bz; 223 // regdst = 1'bz;
224 regwrite = 1'b0; 224 regwrite = 1'b0;
225 - // alusrc = 1'bz; 225 + alusrc = 1'b1;
226 aluctrl = 4'b1111; 226 aluctrl = 4'b1111;
227 memread = 1'b0; 227 memread = 1'b0;
228 memwrite = 1'b0; 228 memwrite = 1'b0;
...@@ -236,7 +236,7 @@ always @(*) begin ...@@ -236,7 +236,7 @@ always @(*) begin
236 6'b000011: begin // jal instruction 236 6'b000011: begin // jal instruction
237 // regdst = 1'bz; 237 // regdst = 1'bz;
238 regwrite = 1'b1; 238 regwrite = 1'b1;
239 - // alusrc = 1'bz; 239 + alusrc = 1'b1;
240 aluctrl = 4'b1111; 240 aluctrl = 4'b1111;
241 memread = 1'b0; 241 memread = 1'b0;
242 memwrite = 1'b0; 242 memwrite = 1'b0;
...@@ -278,7 +278,7 @@ always @(*) begin ...@@ -278,7 +278,7 @@ always @(*) begin
278 default: begin // unknown instruction 278 default: begin // unknown instruction
279 // regdst = 1'bz; 279 // regdst = 1'bz;
280 regwrite = 1'b0; 280 regwrite = 1'b0;
281 - // alusrc = 1'bz; 281 + alusrc = 1'b1;
282 aluctrl = 4'b1111; 282 aluctrl = 4'b1111;
283 memread = 1'b0; 283 memread = 1'b0;
284 memwrite = 1'b0; 284 memwrite = 1'b0;
......
1 -// Data Hazard Handling 1 +// Hazard Handling ( No Fowarding )
2 -module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 2 +module HazardHandling(clk,
3 - in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 3 + in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, // for data hazard handling
4 - out_stallsignal); 4 + in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
5 + in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, // for control hazard handling
6 + out_stallsignal, out_flushsignal, out_nextPC);
5 input clk; 7 input clk;
6 -input in_ex_regwrite, in_mem_regwrite, in_wb_regwrite; 8 +input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch;
7 -input[4:0] in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num; 9 +input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
10 +input[31:0] in_wb_nextPC;
11 +
8 output reg out_stallsignal; 12 output reg out_stallsignal;
13 +output reg[4:0] out_flushsignal;
14 +output reg[31:0] out_nextPC;
9 15
10 -initial out_stallsignal = 1'b0; 16 +reg[4:0] readreg2;
11 17
18 +initial begin
19 + readreg2 <= 5'b00000;
20 + out_stallsignal <= 1'b0;
21 + out_flushsignal <= 5'b00000;
22 + out_nextPC <= 32'h00000000;
23 +end
12 always @(negedge clk) begin 24 always @(negedge clk) begin
13 - if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_readreg_num1 || in_ex_writereg_num==in_readreg_num2)) begin 25 +// Data Hazard Handling
26 + readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
27 + if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
14 out_stallsignal = 1'b1; 28 out_stallsignal = 1'b1;
15 - end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_readreg_num1 || in_mem_writereg_num==in_readreg_num2)) begin 29 + out_flushsignal = 5'b00100;
30 + end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
16 out_stallsignal = 1'b1; 31 out_stallsignal = 1'b1;
17 - end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_readreg_num1 || in_wb_writereg_num==in_readreg_num2)) begin 32 + out_flushsignal = 5'b00100;
33 + end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
18 out_stallsignal = 1'b1; 34 out_stallsignal = 1'b1;
19 - end else out_stallsignal = 1'b0; 35 + out_flushsignal = 5'b00100;
36 + end else begin
37 + out_stallsignal = 1'b0;
38 +
39 +// Control Hazard Handling
40 + if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
41 + else if(in_ex_branch == 1'b1) out_flushsignal = 5'b11100;
42 + else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
43 + out_nextPC = in_wb_nextPC;
44 + out_flushsignal[4] = 1'b0;
45 + end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
46 + end
47 +end
48 +endmodule
49 +
50 +
51 +// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
52 +// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
53 +// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
54 +
55 +
56 +// Hazard Handling ( Fowarding )
57 +// not finished
58 +module HazardHandling_Forwarding(clk,
59 + in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_ex_memtoreg, // for data hazard handling
60 + in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
61 + in_id_jump, in_id_jumpreg, in_ex_jumpreg, in_ex_branch, // for control hazard handling
62 + in_id_PCjump, in_ex_PCjumpreg, in_ex_PCbranch,
63 + out_stallsignal, out_flushsignal, out_fowardsig1, out_fowardsig2, out_nextPC);
64 +input clk;
65 +input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_ex_memtoreg, in_id_jump, in_id_jumpreg, in_ex_jumpreg, in_ex_branch;
66 +input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
67 +input[31:0] in_id_PCjump, in_ex_PCjumpreg, in_ex_PCbranch;
68 +
69 +output reg out_stallsignal;
70 +output reg[1:0] out_fowardsig1, out_fowardsig2;
71 +output reg[4:0] out_flushsignal;
72 +output reg[31:0] out_nextPC;
73 +
74 +reg branchfinished;
75 +reg[4:0] readreg2;
76 +
77 +initial begin
78 + branchfinished = 1'b0;
79 + readreg2 = 5'b00000;
80 + out_stallsignal = 1'b0;
81 + out_flushsignal = 5'b00000;
82 + out_fowardsig1 = 2'b00;
83 + out_fowardsig2 = 2'b00;
84 + out_nextPC = 32'h00000000;
85 +end
86 +always @(negedge clk) begin
87 +// Data Hazard Handling
88 + readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
89 + if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2) && in_ex_memtoreg==1'b1) begin
90 + out_stallsignal = 1'b1;
91 + out_flushsignal = 5'b00100;
92 + end else begin
93 + if(in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000 && in_ex_writereg_num==in_id_readreg_num1 && in_ex_memtoreg==1'b0) out_fowardsig1 = 2'b01;
94 + else if(in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000 && in_mem_writereg_num==in_id_readreg_num1) out_fowardsig1 = 2'b10;
95 + else if(in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000 && in_wb_writereg_num==in_id_readreg_num1) out_fowardsig1 = 2'b11;
96 + else out_fowardsig1 = 2'b00;
97 +
98 + if(in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000 && in_ex_writereg_num==readreg2 && in_ex_memtoreg==1'b0) out_fowardsig2 = 2'b01;
99 + else if(in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000 && in_mem_writereg_num==readreg2) out_fowardsig2 = 2'b10;
100 + else if(in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000 && in_wb_writereg_num==readreg2) out_fowardsig2 = 2'b11;
101 + else out_fowardsig2 = 2'b00;
102 +
103 +// Control Hazard Handling
104 + if(branchfinished == 1'b1) begin
105 + out_flushsignal[4] = 1'b0;
106 + branchfinished = 1'b0;
107 + end else if(in_id_jump == 1'b1 && in_id_jumpreg == 1'b0) begin
108 + out_nextPC = in_id_PCjump;
109 + out_flushsignal = 5'b11000;
110 + branchfinished = 1'b1;
111 + end else if(in_ex_jumpreg == 1'b1) begin
112 + out_nextPC = in_ex_PCjumpreg;
113 + out_flushsignal = 5'b11100;
114 + branchfinished = 1'b1;
115 + end else if(in_ex_branch == 1'b1) begin
116 + out_nextPC = in_ex_PCbranch;
117 + out_flushsignal = 5'b11100;
118 + branchfinished = 1'b1;
119 + end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
120 + end
20 end 121 end
122 +endmodule
123 +
124 +module Mux_Forwarding(input1, input2, input3, input4, signal, output1);
125 +input[31:0] input1, input2, input3, input4;
126 +input[1:0] signal;
127 +output reg[31:0] output1;
21 128
129 +always @(*) begin
130 + case(signal)
131 + 2'b00: output1 <= input1;
132 + 2'b01: output1 <= input2;
133 + 2'b10: output1 <= input3;
134 + 2'b11: output1 <= input4;
135 + endcase
136 +end
22 endmodule 137 endmodule
23 138
24 139
140 +
141 +
25 // Control Hazard Handling 142 // Control Hazard Handling
26 -module Flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch, 143 +/*
27 - out_flush_jump, out_flush_branch, out_pc); 144 +module Flush_fowarding(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch,
145 + out_flush, out_pc);
28 input clk; 146 input clk;
29 147
30 input ctrl_jump, ctrl_jumpreg, ex_branchsignal; 148 input ctrl_jump, ctrl_jumpreg, ex_branchsignal;
31 input[2:0] ctrl_branch; 149 input[2:0] ctrl_branch;
32 input[31:0] pc_jump, pc_jumpreg, ex_pc_branch; 150 input[31:0] pc_jump, pc_jumpreg, ex_pc_branch;
33 151
34 -output reg out_flush_jump, out_flush_branch; 152 +output reg[4:0] out_flush;
35 output reg[31:0] out_pc; 153 output reg[31:0] out_pc;
36 154
37 reg isbranch; 155 reg isbranch;
38 156
39 initial begin 157 initial begin
40 isbranch = 1'b0; 158 isbranch = 1'b0;
41 - out_flush_jump = 1'b0; 159 + out_flush = 5'b00000;
42 - out_flush_branch = 1'b0;
43 out_pc = 32'h00000000; 160 out_pc = 32'h00000000;
44 end 161 end
45 162
...@@ -47,17 +164,16 @@ always @(negedge clk) begin ...@@ -47,17 +164,16 @@ always @(negedge clk) begin
47 if(isbranch == 1'b1) begin 164 if(isbranch == 1'b1) begin
48 if(ex_branchsignal == 1'b1) begin 165 if(ex_branchsignal == 1'b1) begin
49 out_pc = ex_pc_branch; 166 out_pc = ex_pc_branch;
50 - out_flush_branch = 1'b1; 167 + out_flush = 5'b11100;
51 - end 168 + end
52 isbranch = 1'b0; 169 isbranch = 1'b0;
53 end else begin 170 end else begin
54 - out_flush_branch = 1'b0;
55 -
56 if(ctrl_jump == 1'b1) begin 171 if(ctrl_jump == 1'b1) begin
57 - out_flush_jump = 1'b1; 172 + out_flush = 5'b11000;
58 out_pc = (ctrl_jumpreg == 1'b0) ? pc_jump : pc_jumpreg; 173 out_pc = (ctrl_jumpreg == 1'b0) ? pc_jump : pc_jumpreg;
59 end else if(ctrl_branch != 3'b000) isbranch = 1'b1; 174 end else if(ctrl_branch != 3'b000) isbranch = 1'b1;
60 - else out_flush_jump = 1'b0; 175 + else out_flush = 5'b00000;
61 end 176 end
62 end 177 end
63 endmodule 178 endmodule
179 +*/
...\ No newline at end of file ...\ No newline at end of file
......
...@@ -6,37 +6,48 @@ output reg[31:0] instruction; ...@@ -6,37 +6,48 @@ output reg[31:0] instruction;
6 reg[31:0] instr_mem[127:0]; 6 reg[31:0] instr_mem[127:0];
7 /* 7 /*
8 initial begin 8 initial begin
9 +
10 +end
11 +*/
12 +/*
13 +initial begin
9 instr_mem[0] = 32'd0; 14 instr_mem[0] = 32'd0;
10 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 15 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
11 -instr_mem[2] = 32'd0; 16 +instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
12 -instr_mem[3] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 17 +instr_mem[3] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
13 instr_mem[4] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 18 instr_mem[4] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
14 -instr_mem[5] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 19 +instr_mem[5] = 32'd0;
15 -instr_mem[6] = 32'b00100100000011010000000000000011; // addi, $0 $13 3 20 +instr_mem[6] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
16 -instr_mem[7] = 32'b00100100000010010000000000000001; // addi, $0 $9 1 21 +instr_mem[7] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
17 -instr_mem[8] = 32'b10101100000011010000000000111100; // sw, $0 $13 60 22 +instr_mem[8] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
18 instr_mem[9] = 32'd0; 23 instr_mem[9] = 32'd0;
24 +instr_mem[10] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
25 +instr_mem[11] = 32'b00100100000010010000000000000001; // addi, $0 $9 1
26 +instr_mem[12] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
27 +instr_mem[13] = 32'd0;
19 end 28 end
20 */ 29 */
21 30
22 initial begin 31 initial begin
23 -instr_mem[0] = 32'd0; 32 +instr_mem[0] = 32'b00100111000110000000000111111111; // addi, $24 $24 511
24 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 33 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
25 instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 34 instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
26 instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9 35 instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9
27 instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10 36 instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10
28 -instr_mem[5] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1 37 +instr_mem[5] = 32'b00010001000010100000000000000101; // beq, $8 $10 +5
29 -instr_mem[6] = 32'b00000001000000000111100000100000; // add, $8 $0 $15 38 +instr_mem[6] = 32'b00000001000010010000000000011000; // mult, $8 $9
30 -instr_mem[7] = 32'b00000001000010010000000000011000; // mult, $8 $9 39 +instr_mem[7] = 32'b00000001000000000111100000100000; // add, $8 $0 $15
31 instr_mem[8] = 32'd0; 40 instr_mem[8] = 32'd0;
32 instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12 41 instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12
33 instr_mem[10] = 32'b00000000000000000110100000010010; // mflo, $13 42 instr_mem[10] = 32'b00000000000000000110100000010010; // mflo, $13
34 -instr_mem[11] = 32'b10101100000011010000000000111100; // sw, $0 $13 60 43 +instr_mem[11] = 32'b10101100000010010000000000111100; // sw, $0 $9 60
35 instr_mem[12] = 32'd0; 44 instr_mem[12] = 32'd0;
36 instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1 45 instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
37 instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60 46 instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
38 -instr_mem[15] = 32'b00001100000000000000000000010000; // jal, 16 47 +instr_mem[15] = 32'b00001100000000000000000000010001; // jal, 17
39 -instr_mem[16] = 32'b00000000000000000000000000001000; // jr, $0 48 +instr_mem[16] = 32'b00000001000010010000000000011000; // mult, $8 $9
49 +instr_mem[17] = 32'b00000000000000000000000000001000; // jr, $0
50 +instr_mem[18] = 32'b00000001000010010000000000011000; // mult, $8 $9
40 end 51 end
41 52
42 always @ (*) begin 53 always @ (*) begin
......
...@@ -5,6 +5,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -5,6 +5,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
5 Top level modules: 5 Top level modules:
6 Adder 6 Adder
7 7
8 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
9 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 +-- Compiling module MIPS_Pipeline_Forwarding
11 +
12 +Top level modules:
13 + MIPS_Pipeline_Forwarding
14 +
8 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 15 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 16 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 -- Compiling module MIPS_SingleCycle 17 -- Compiling module MIPS_SingleCycle
...@@ -26,36 +33,38 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -26,36 +33,38 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
26 Top level modules: 33 Top level modules:
27 Register 34 Register
28 35
29 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
30 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
31 --- Compiling module MIPS_Pipeline
32 -
33 -Top level modules:
34 - MIPS_Pipeline
35 -
36 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 36 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
37 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 37 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
38 +-- Compiling module PCregister
38 -- Compiling module IF_ID 39 -- Compiling module IF_ID
39 -- Compiling module ID_EX 40 -- Compiling module ID_EX
40 -- Compiling module EX_MEM 41 -- Compiling module EX_MEM
41 -- Compiling module MEM_WB 42 -- Compiling module MEM_WB
42 --- Compiling module PCcounter
43 43
44 Top level modules: 44 Top level modules:
45 + PCregister
45 IF_ID 46 IF_ID
46 ID_EX 47 ID_EX
47 EX_MEM 48 EX_MEM
48 MEM_WB 49 MEM_WB
49 - PCcounter 50 +
51 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
52 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
53 +-- Compiling module MIPS_Pipeline
54 +
55 +Top level modules:
56 + MIPS_Pipeline
50 57
51 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 58 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
52 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 59 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
53 --- Compiling module Stall 60 +-- Compiling module HazardHandling
54 --- Compiling module Flush 61 +-- Compiling module HazardHandling_Forwarding
62 +-- Compiling module Mux_Forwarding
55 63
56 Top level modules: 64 Top level modules:
57 - Stall 65 + HazardHandling
58 - Flush 66 + HazardHandling_Forwarding
67 + Mux_Forwarding
59 68
60 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 69 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
61 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 70 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -106,8 +115,10 @@ Top level modules: ...@@ -106,8 +115,10 @@ Top level modules:
106 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v 115 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
107 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 116 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
108 -- Compiling module Clock 117 -- Compiling module Clock
118 +-- Compiling module Clock_pipeline
109 119
110 Top level modules: 120 Top level modules:
111 Clock 121 Clock
122 + Clock_pipeline
112 123
113 } {} {}} 124 } {} {}}
......
This diff is collapsed. Click to expand it.
1 -// Test Required
2 module MIPS_Pipeline; 1 module MIPS_Pipeline;
3 -
4 wire clk; 2 wire clk;
5 -wire stallsignal; 3 +wire[31:0] _PC, addPC4, addPCbranch, tempPC_branch, tempPC_jump, PC_branch, nextPC;
6 -wire flush_jump, flush_branch;
7 -wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC, flush_pc;
8 4
9 wire[31:0] instr; // loaded instruction. 5 wire[31:0] instr; // loaded instruction.
10 6
...@@ -44,24 +40,30 @@ wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_ ...@@ -44,24 +40,30 @@ wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_
44 40
45 // MEM_WB register outputs 41 // MEM_WB register outputs
46 wire[4:0] memwb_writereg1; 42 wire[4:0] memwb_writereg1;
47 -wire memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link; 43 +wire memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link;
48 -wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch; 44 +wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch;
45 +
46 +// Hazard Handling Outputs
47 +wire stallsignal;
48 +wire[4:0] flushsignal;
49 +wire[31:0] flush_nextPC;
49 50
50 -wire temp; 51 +Clock_pipeline clock(clk);
51 -assign temp = 1'b0; 52 +PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
52 53
53 -Clock clock(clk); 54 +// Hazard Handling (No Fowarding)
54 -PCcounter pccounter(clk, stallsignal, (flush_jump|flush_branch), flush_pc, instr_address); 55 +HazardHandling hazardhandling(clk,
55 -Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, stallsignal); 56 + ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, // for data hazard handling
56 -Flush flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, branch_signal, {ifid_PC_4[31:28], shiftJump_output[27:0]}, reg_readdata1, addPCbranch, 57 + ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,
57 - flush_jump, flush_branch, flush_pc); 58 + ctrl_jump, branch_signal, memwb_jump, memwb_branch, nextPC,
59 + stallsignal, flushsignal, flush_nextPC);
58 60
59 // Instruction Fetch 61 // Instruction Fetch
60 -InstructionMemory instrmem(instr_address, instr); 62 +InstructionMemory instrmem(_PC, instr);
61 -Adder add_pc4(instr_address, 32'h00000004, addPC4); 63 +Adder add_pc4(_PC, 32'h00000004, addPC4);
62 64
63 -IF_ID ifid(clk, stallsignal, 65 +IF_ID ifid(clk, stallsignal, flushsignal[3],
64 - (flush_jump|flush_branch), instr, addPC4, 66 + instr, addPC4,
65 ifid_instr, ifid_PC_4); 67 ifid_instr, ifid_PC_4);
66 68
67 // Instruction Decode 69 // Instruction Decode
...@@ -73,7 +75,7 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re ...@@ -73,7 +75,7 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re
73 SignExtend extend(ifid_instr[15:0], extend_output); 75 SignExtend extend(ifid_instr[15:0], extend_output);
74 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output); 76 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
75 77
76 -ID_EX idex(clk, stallsignal, flush_branch, 78 +ID_EX idex(clk, flushsignal[2],
77 reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link, 79 reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link,
78 reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, 80 reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output,
79 idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link, 81 idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link,
...@@ -87,27 +89,28 @@ Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch); ...@@ -87,27 +89,28 @@ Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
87 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal); 89 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal);
88 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump); 90 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump);
89 91
90 -EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link, 92 +EX_MEM ex_mem(clk, flushsignal[1],
93 + idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link,
91 alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 94 alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch,
92 exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 95 exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link,
93 exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch); 96 exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
94 97
95 // Memory 98 // Memory
96 DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exmem_memwrite, mem_readdata); 99 DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exmem_memwrite, mem_readdata);
97 -Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch);
98 100
99 -MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, exmem_link, 101 +MEM_WB mem_wb(clk, flushsignal[0],
100 - exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, tempPC_branch, 102 + exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link,
101 - memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link, 103 + exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch,
102 - memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch); 104 + memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link,
105 + memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch);
103 106
104 // Writeback 107 // Writeback
105 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, temp_writedata); 108 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, temp_writedata);
106 Mux32bit mux_link_data(temp_writedata, memwb_PC_4, memwb_link, reg_writedata); 109 Mux32bit mux_link_data(temp_writedata, memwb_PC_4, memwb_link, reg_writedata);
107 -Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC); 110 +Mux32bit mux_branch(memwb_PC_4, memwb_tempPCbranch, memwb_branch , PC_branch);
111 +Mux32bit mux_jump(PC_branch, memwb_PCjump, memwb_jump, nextPC);
108 112
109 113
110 -always @(posedge clk) begin 114 +always @(posedge clk) begin end
111 -end
112 115
113 endmodule 116 endmodule
......
1 +// Test Required
2 +module MIPS_Pipeline_Forwarding;
3 +wire clk;
4 +wire[31:0] _PC, addPC4, addPCbranch, tempPC_branch, tempPC_jump, PC_branch, nextPC;
5 +
6 +wire[31:0] instr; // loaded instruction.
7 +
8 +wire[4:0] temp_writereg, reg_writereg1; // register number for the write data.
9 +wire[31:0] temp_writedata, reg_writedata; // data that will be written in the register.
10 +wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
11 +
12 +wire[31:0] alu_input2; // input data of ALU.
13 +wire[31:0] alu_result; // result data of ALU.
14 +wire[5:0] alu_branch; // indicator for branch operation.
15 +
16 +wire[31:0] mem_readdata; // data from the requested address.
17 +
18 +wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
19 +wire[3:0] ctrl_aluctrl; // control signals.
20 +wire[2:0] ctrl_branch;
21 +
22 +wire[31:0] extend_output;
23 +
24 +wire[31:0] shiftBranch_output;
25 +wire[31:0] shiftJump_output;
26 +
27 +// IF_ID register outputs
28 +wire[31:0] ifid_instr, ifid_PC_4;
29 +
30 +// ID_EX register outputs
31 +wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
32 +wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg, idex_link;
33 +wire[3:0] idex_aluctrl;
34 +wire[2:0] idex_branch;
35 +wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;
36 +
37 +// EX_MEM register outputs
38 +wire[4:0] exmem_writereg1;
39 +wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link;
40 +wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;
41 +
42 +// MEM_WB register outputs
43 +wire[4:0] memwb_writereg1;
44 +wire memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link;
45 +wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch;
46 +
47 +// Hazard Handling Outputs
48 +wire stallsignal;
49 +wire[4:0] flushsignal;
50 +wire[1:0] fowardsig1, fowardsig2;
51 +wire[31:0] flush_nextPC;
52 +// Forwarding Mux Outputs
53 +wire[31:0] forwarding_mem_writeregdata, forwarding_id_readdata1, forwarding_id_readdata2;
54 +
55 +Clock_pipeline clock(clk);
56 +PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
57 +
58 +// Hazard Handling (Fowarding) not finished
59 +HazardHandling_Forwarding hazardhandling(clk,
60 + ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, idex_memtoreg, // for data hazard handling
61 + ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,
62 + ctrl_jump, ctrl_jumpreg, idex_jumpreg, branch_signal, // for control hazard handling
63 + {ifid_PC_4[31:28], shiftJump_output[27:0]}, idex_readdata1, addPCbranch,
64 + stallsignal, flushsignal, fowardsig1, fowardsig2, flush_nextPC);
65 +
66 +
67 +// Instruction Fetch
68 +InstructionMemory instrmem(_PC, instr);
69 +Adder add_pc4(_PC, 32'h00000004, addPC4);
70 +
71 +IF_ID ifid(clk, stallsignal, flushsignal[3],
72 + instr, addPC4,
73 + ifid_instr, ifid_PC_4);
74 +
75 +// Instruction Decode
76 +Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0],
77 + ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
78 +Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11], ctrl_regdst, temp_writereg);
79 +Mux5bit mux_link_reg(temp_writereg, 5'b11111, ctrl_link, reg_writereg1);
80 +Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata, memwb_regwrite, reg_readdata1, reg_readdata2);
81 +SignExtend extend(ifid_instr[15:0], extend_output);
82 +ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
83 +
84 + // forwarding mux
85 +Mux32bit mux_forwarding_mem(exmem_aluresult, mem_readdata, exmem_memtoreg, forwarding_mem_writeregdata);
86 +Mux_Forwarding mux_forwrading1(reg_readdata1, alu_result, forwarding_mem_writeregdata, reg_writedata, fowardsig1, forwarding_id_readdata1);
87 +Mux_Forwarding mux_forwrading2(reg_readdata2, alu_result, forwarding_mem_writeregdata, reg_writedata, fowardsig2, forwarding_id_readdata2);
88 +
89 +ID_EX idex(clk, flushsignal[2],
90 + reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link,
91 + forwarding_id_readdata1, forwarding_id_readdata2, extend_output, ifid_PC_4, shiftJump_output,
92 + idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link,
93 + idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
94 +
95 +// Execute
96 +Mux32bit mux_alusrc(idex_readdata2, idex_extenddata, idex_alusrc, alu_input2);
97 +ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch);
98 +ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
99 +Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
100 +MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal);
101 +Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump);
102 +
103 +EX_MEM ex_mem(clk, flushsignal[1],
104 + idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link,
105 + alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch,
106 + exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link,
107 + exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
108 +
109 +// Memory
110 +DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exmem_memwrite, mem_readdata);
111 +
112 +MEM_WB mem_wb(clk, flushsignal[0],
113 + exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link,
114 + exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch,
115 + memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link,
116 + memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch);
117 +
118 +// Writeback
119 +Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, temp_writedata);
120 +Mux32bit mux_link_data(temp_writedata, memwb_PC_4, memwb_link, reg_writedata);
121 +Mux32bit mux_branch(memwb_PC_4, memwb_tempPCbranch, memwb_branch , PC_branch);
122 +Mux32bit mux_jump(PC_branch, memwb_PCjump, memwb_jump, nextPC);
123 +
124 +
125 +always @(posedge clk) begin end
126 +
127 +endmodule
...@@ -49,6 +49,7 @@ Adder add_branch(addPC4, shiftBranch_output, addPCbranch); ...@@ -49,6 +49,7 @@ Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
49 ShiftLeft2 shiftBranch(extend_output, shiftBranch_output); 49 ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
50 ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output); 50 ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
51 51
52 +// PC Register
52 initial begin 53 initial begin
53 PC = 32'h00000000; 54 PC = 32'h00000000;
54 end 55 end
......
1 +module PCregister(clk, stall, flush, in_pc, out_nextpc);
2 +input clk, stall, flush;
3 +
4 +input[31:0] in_pc;
5 +output reg[31:0] out_nextpc;
6 +
7 +reg[31:0] PC;
8 +reg tempstall;
9 +
10 +initial begin
11 + PC = 32'h00000000;
12 + tempstall = 1'b1;
13 +end
14 +
15 +always @(posedge clk) begin
16 + if(tempstall == 1'b1) tempstall = 1'b0;
17 + else if(stall == 1'b0 && flush == 1'b0) PC = PC+4;
18 + out_nextpc = PC;
19 +end
20 +always @(negedge flush) begin
21 + if(tempstall == 1'b0) PC = in_pc;
22 + tempstall = 1'b1;
23 +end
24 +endmodule
25 +
26 +
1 module IF_ID(clk, stall, flush, in_instruction, in_PC_4, 27 module IF_ID(clk, stall, flush, in_instruction, in_PC_4,
2 out_instruction, out_PC_4); 28 out_instruction, out_PC_4);
3 input clk, stall, flush; 29 input clk, stall, flush;
...@@ -7,36 +33,15 @@ input[31:0] in_instruction, in_PC_4; ...@@ -7,36 +33,15 @@ input[31:0] in_instruction, in_PC_4;
7 output reg[31:0] out_instruction, out_PC_4; 33 output reg[31:0] out_instruction, out_PC_4;
8 34
9 reg[31:0] temp_instruction, temp_PC_4; 35 reg[31:0] temp_instruction, temp_PC_4;
10 - 36 +
11 -reg first, stallfinished, flushed;
12 -
13 -initial begin
14 - first = 1'b1;
15 - stallfinished = 1'b0;
16 - flushed = 1'b0;
17 -end
18 always @(posedge clk) begin 37 always @(posedge clk) begin
19 if(stall == 1'b1) begin 38 if(stall == 1'b1) begin
20 out_instruction <= temp_instruction; 39 out_instruction <= temp_instruction;
21 - out_PC_4 <= temp_PC_4; 40 + out_PC_4 <= temp_PC_4;
22 - end 41 + end else if(flush == 1'b1) begin
23 - else if(flush == 1'b1) begin
24 out_instruction <= 32'h00000000; 42 out_instruction <= 32'h00000000;
25 out_PC_4 <= 32'h00000000; 43 out_PC_4 <= 32'h00000000;
26 - end 44 + end else begin
27 - else if(flushed == 1'b1) begin
28 - out_instruction <= 32'h00000000;
29 - out_PC_4 <= 32'h00000000;
30 - stallfinished = 1'b0;
31 - flushed = 1'b0;
32 - end
33 - else if(stallfinished == 1'b1) begin
34 - out_instruction <= temp_instruction;
35 - out_PC_4 <= temp_PC_4;
36 - stallfinished = 1'b0;
37 - flushed = 1'b0;
38 - end
39 - else begin
40 out_instruction <= in_instruction; 45 out_instruction <= in_instruction;
41 out_PC_4 <= in_PC_4; 46 out_PC_4 <= in_PC_4;
42 end 47 end
...@@ -45,17 +50,15 @@ always @(posedge stall) begin ...@@ -45,17 +50,15 @@ always @(posedge stall) begin
45 temp_instruction <= out_instruction; 50 temp_instruction <= out_instruction;
46 temp_PC_4 <= out_PC_4; 51 temp_PC_4 <= out_PC_4;
47 end 52 end
48 -always @(negedge stall) stallfinished = 1'b1;
49 -always @(negedge flush) flushed = 1'b1;
50 endmodule 53 endmodule
51 54
52 55
53 -module ID_EX(clk, stall, flush, 56 +module ID_EX(clk, flush,
54 in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, in_link, 57 in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, in_link,
55 in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, 58 in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump,
56 out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, out_link, 59 out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, out_link,
57 out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump); 60 out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
58 -input clk, stall, flush; 61 +input clk, flush;
59 62
60 input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2; 63 input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
61 input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg, in_link; 64 input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg, in_link;
...@@ -69,33 +72,8 @@ output reg[3:0] out_aluctrl; ...@@ -69,33 +72,8 @@ output reg[3:0] out_aluctrl;
69 output reg[2:0] out_branch; 72 output reg[2:0] out_branch;
70 output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump; 73 output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
71 74
72 -reg stallfinished;
73 -
74 -initial stallfinished = 1'b0;
75 always @(posedge clk) begin 75 always @(posedge clk) begin
76 - if(stall == 1'b1 || flush == 1'b1) begin 76 + if(flush == 1'b1) begin
77 - out_writereg_num <= 5'b00000;
78 - out_readreg_num1 <= 5'b00000;
79 - out_readreg_num2 <= 5'b00000;
80 -
81 - out_regwrite <= 1'b0;
82 - out_alusrc <= 1'b0;
83 - out_aluctrl <= 4'b0000;
84 - out_memread <= 1'b0;
85 - out_memwrite <= 1'b0;
86 - out_memtoreg <= 1'b0;
87 - out_branch <= 3'b000;
88 - out_jump <= 1'b0;
89 - out_jumpreg <= 1'b0;
90 - out_link <= 1'b0;
91 -
92 - out_readdata1 <= 32'h00000000;
93 - out_readdata2 <= 32'h00000000;
94 - out_extenddata <= 32'h00000000;
95 - out_PC_4 <= 32'h00000000;
96 - out_tempPCjump <= 32'h00000000;
97 - end
98 - else if(stallfinished == 1'b1) begin
99 out_writereg_num <= 5'b00000; 77 out_writereg_num <= 5'b00000;
100 out_readreg_num1 <= 5'b00000; 78 out_readreg_num1 <= 5'b00000;
101 out_readreg_num2 <= 5'b00000; 79 out_readreg_num2 <= 5'b00000;
...@@ -116,10 +94,7 @@ always @(posedge clk) begin ...@@ -116,10 +94,7 @@ always @(posedge clk) begin
116 out_extenddata <= 32'h00000000; 94 out_extenddata <= 32'h00000000;
117 out_PC_4 <= 32'h00000000; 95 out_PC_4 <= 32'h00000000;
118 out_tempPCjump <= 32'h00000000; 96 out_tempPCjump <= 32'h00000000;
119 - 97 + end else begin
120 - stallfinished = 1'b0;
121 - end
122 - else begin
123 out_writereg_num <= in_writereg_num; 98 out_writereg_num <= in_writereg_num;
124 out_readreg_num1 <= in_readreg_num1; 99 out_readreg_num1 <= in_readreg_num1;
125 out_readreg_num2 <= in_readreg_num2; 100 out_readreg_num2 <= in_readreg_num2;
...@@ -142,15 +117,14 @@ always @(posedge clk) begin ...@@ -142,15 +117,14 @@ always @(posedge clk) begin
142 out_tempPCjump <= in_tempPCjump; 117 out_tempPCjump <= in_tempPCjump;
143 end 118 end
144 end 119 end
145 -always @(negedge stall or negedge flush) stallfinished = 1'b1;
146 endmodule 120 endmodule
147 121
148 122
149 -module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link, 123 +module EX_MEM(clk, flush, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link,
150 in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 124 in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch,
151 out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link, 125 out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link,
152 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch); 126 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
153 -input clk; 127 +input clk, flush;
154 128
155 input[4:0] in_writereg_num; 129 input[4:0] in_writereg_num;
156 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link; 130 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link;
...@@ -160,70 +134,80 @@ output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, ou ...@@ -160,70 +134,80 @@ output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, ou
160 output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch; 134 output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;
161 135
162 always @(posedge clk) begin 136 always @(posedge clk) begin
163 - out_writereg_num <= in_writereg_num; 137 + if(flush == 1'b1) begin
164 - out_regwrite <= in_regwrite; 138 + out_writereg_num <= 5'b00000;
165 - out_memread <= in_memread; 139 + out_regwrite <= 1'b0;
166 - out_memwrite <= in_memwrite; 140 + out_memread <= 1'b0;
167 - out_memtoreg <= in_memtoreg; 141 + out_memwrite <= 1'b0;
168 - out_branch <= in_branch; 142 + out_memtoreg <= 1'b0;
169 - out_jump <= in_jump; 143 + out_branch <= 1'b0;
170 - out_link <= in_link; 144 + out_jump <= 1'b0;
171 - 145 + out_link <= 1'b0;
172 - out_aluresult <= in_aluresult; 146 +
173 - out_mem_writedata <= in_mem_writedata; 147 + out_aluresult <= 32'h00000000;
174 - out_PC_4 <= in_PC_4; 148 + out_mem_writedata <= 32'h00000000;
175 - out_PCjump <= in_PCjump; 149 + out_PC_4 <= 32'h00000000;
176 - out_tempPCbranch <= in_tempPCbranch; 150 + out_PCjump <= 32'h00000000;
151 + out_tempPCbranch <= 32'h00000000;
152 + end else begin
153 + out_writereg_num <= in_writereg_num;
154 + out_regwrite <= in_regwrite;
155 + out_memread <= in_memread;
156 + out_memwrite <= in_memwrite;
157 + out_memtoreg <= in_memtoreg;
158 + out_branch <= in_branch;
159 + out_jump <= in_jump;
160 + out_link <= in_link;
161 +
162 + out_aluresult <= in_aluresult;
163 + out_mem_writedata <= in_mem_writedata;
164 + out_PC_4 <= in_PC_4;
165 + out_PCjump <= in_PCjump;
166 + out_tempPCbranch <= in_tempPCbranch;
167 + end
177 end 168 end
178 endmodule 169 endmodule
179 170
180 171
181 -module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_link, in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch, 172 +module MEM_WB(clk, flush, in_writereg_num, in_regwrite, in_memtoreg, in_branch, in_jump, in_link, in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch,
182 - out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_link, out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch); 173 + out_writereg_num, out_regwrite, out_memtoreg, out_branch, out_jump, out_link, out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch);
183 -input clk; 174 +input clk, flush;
184 175
185 input[4:0] in_writereg_num; 176 input[4:0] in_writereg_num;
186 -input in_regwrite, in_memtoreg, in_jump, in_link; 177 +input in_regwrite, in_memtoreg, in_branch, in_jump, in_link;
187 input[31:0] in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch; 178 input[31:0] in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch;
188 output reg[4:0] out_writereg_num; 179 output reg[4:0] out_writereg_num;
189 -output reg out_regwrite, out_memtoreg, out_jump, out_link; 180 +output reg out_regwrite, out_memtoreg, out_branch, out_jump, out_link;
190 output reg[31:0] out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch; 181 output reg[31:0] out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch;
191 182
192 always @(posedge clk) begin 183 always @(posedge clk) begin
193 - out_writereg_num <= in_writereg_num; 184 + if(flush == 1'b1) begin
194 - out_regwrite <= in_regwrite; 185 + out_writereg_num <= 5'b00000;
195 - out_memtoreg <= in_memtoreg; 186 + out_regwrite <= 1'b0;
196 - out_jump <= in_jump; 187 + out_memtoreg <= 1'b0;
197 - out_link <= in_link; 188 + out_branch <= 1'b0;
198 - 189 + out_jump <= 1'b0;
199 - out_aluresult <= in_aluresult; 190 + out_link <= 1'b0;
200 - out_memreaddata <= in_memreaddata;
201 - out_PC_4 <= in_PC_4;
202 - out_PCjump <= in_PCjump;
203 - out_PCbranch <= in_PCbranch;
204 -end
205 -endmodule
206 -
207 -/* Not Finished */
208 -module PCcounter(clk, stall, flush, in_pc, out_nextpc);
209 -input clk, stall, flush;
210 -
211 -input[31:0] in_pc;
212 -output reg[31:0] out_nextpc;
213 -
214 -reg[31:0] PC;
215 -reg stallfinished;
216 191
217 -initial begin 192 + out_aluresult <= 32'h00000000;
218 - PC = 32'h00000000; 193 + out_memreaddata <= 32'h00000000;
219 - stallfinished = 1'b1; 194 + out_PC_4 <= 32'h00000000;
220 -end 195 + out_PCjump <= 32'h00000000;
196 + out_PCbranch <= 32'h00000000;
197 + end else begin
198 + out_writereg_num <= in_writereg_num;
199 + out_regwrite <= in_regwrite;
200 + out_memtoreg <= in_memtoreg;
201 + out_branch <= in_branch;
202 + out_jump <= in_jump;
203 + out_link <= in_link;
221 204
222 -always @(posedge clk) begin 205 + out_aluresult <= in_aluresult;
223 - if(stallfinished == 1'b1) stallfinished = 1'b0; 206 + out_memreaddata <= in_memreaddata;
224 - else if(stall == 1'b0 && flush == 1'b0) PC = PC+4; 207 + out_PC_4 <= in_PC_4;
225 - out_nextpc = PC; 208 + out_PCjump <= in_PCjump;
209 + out_PCbranch <= in_PCbranch;
210 + end
226 end 211 end
227 -always @(negedge stall or negedge flush) stallfinished = 1'b1;
228 -always @(posedge flush) PC = in_pc;
229 endmodule 212 endmodule
213 +
......
...@@ -4,6 +4,14 @@ output reg clk; ...@@ -4,6 +4,14 @@ output reg clk;
4 4
5 initial clk = 0; 5 initial clk = 0;
6 always #50 clk = ~clk; 6 always #50 clk = ~clk;
7 +endmodule
8 +
9 +
10 +module Clock_pipeline(clk);
7 11
12 +output reg clk;
13 +
14 +initial clk = 0;
15 +always #11 clk = ~clk;
8 endmodule 16 endmodule
9 17
......
No preview for this file type
...@@ -9,7 +9,7 @@ z2 ...@@ -9,7 +9,7 @@ z2
9 cModel Technology 9 cModel Technology
10 dC:/Modeltech_pe_edu_10.4a/examples 10 dC:/Modeltech_pe_edu_10.4a/examples
11 vAdder 11 vAdder
12 -Z0 !s110 1591983139 12 +Z0 !s110 1592304743
13 !i10b 1 13 !i10b 1
14 !s100 LKl?GBS:oo[A[hLP0Qb^_1 14 !s100 LKl?GBS:oo[A[hLP0Qb^_1
15 IlbJEP?2C3Ya>zhzD12^S]1 15 IlbJEP?2C3Ya>zhzD12^S]1
...@@ -23,7 +23,7 @@ Z3 OP;L;10.4a;61 ...@@ -23,7 +23,7 @@ Z3 OP;L;10.4a;61
23 r1 23 r1
24 !s85 0 24 !s85 0
25 31 25 31
26 -Z4 !s108 1591983139.000000 26 +Z4 !s108 1592304743.000000
27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
29 !s101 -O0 29 !s101 -O0
...@@ -31,13 +31,13 @@ Z4 !s108 1591983139.000000 ...@@ -31,13 +31,13 @@ Z4 !s108 1591983139.000000
31 Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0 31 Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
32 n@adder 32 n@adder
33 vALU 33 vALU
34 -R0 34 +Z6 !s110 1592304744
35 !i10b 1 35 !i10b 1
36 !s100 z[hZ0^@Q34FnkzY3g0ioc2 36 !s100 z[hZ0^@Q34FnkzY3g0ioc2
37 ImZ3]6XT73YVLGl?0_=9k33 37 ImZ3]6XT73YVLGl?0_=9k33
38 R1 38 R1
39 R2 39 R2
40 -w1591452276 40 +w1592238365
41 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 41 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
42 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 42 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
43 L0 1 43 L0 1
...@@ -53,35 +53,57 @@ R4 ...@@ -53,35 +53,57 @@ R4
53 R5 53 R5
54 n@a@l@u 54 n@a@l@u
55 vClock 55 vClock
56 -R0 56 +R6
57 !i10b 1 57 !i10b 1
58 -!s100 OWQXV6kDYiT>ChTOoCFa]2 58 +!s100 i65lY=7B8[4>bmAoJ2kDB2
59 -IQ?l7WoBBid7ozVDn[8k:e3 59 +I0GMR?JQ97PaC17BI<HeS82
60 R1 60 R1
61 R2 61 R2
62 -w1591110854 62 +Z7 w1592091089
63 -8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v 63 +Z8 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
64 -FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v 64 +Z9 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
65 L0 1 65 L0 1
66 R3 66 R3
67 r1 67 r1
68 !s85 0 68 !s85 0
69 31 69 31
70 -R4 70 +Z10 !s108 1592304744.000000
71 -!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v| 71 +Z11 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
72 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v| 72 +Z12 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
73 !s101 -O0 73 !s101 -O0
74 !i113 1 74 !i113 1
75 R5 75 R5
76 n@clock 76 n@clock
77 +vClock_pipeline
78 +R6
79 +!i10b 1
80 +!s100 dPQB6MR4Y;CLL9a@O1o1B0
81 +I7@GBo9UQ711@mL4ZBf;@Z1
82 +R1
83 +R2
84 +R7
85 +R8
86 +R9
87 +L0 10
88 +R3
89 +r1
90 +!s85 0
91 +31
92 +R10
93 +R11
94 +R12
95 +!s101 -O0
96 +!i113 1
97 +R5
98 +n@clock_pipeline
77 vControl 99 vControl
78 -Z6 !s110 1591983140 100 +R6
79 !i10b 1 101 !i10b 1
80 -!s100 NdQKEjPCPSHG<0<4CTgfz1 102 +!s100 PKg@cjO2lUjfUI`iaE9QB2
81 -Io?;>IIVLB=Zl;M_TSQZ9I2 103 +IX2Ii?h^g2a@DaCi9:L8BU1
82 R1 104 R1
83 R2 105 R2
84 -w1591975942 106 +w1592280009
85 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 107 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
86 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 108 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
87 L0 1 109 L0 1
...@@ -89,7 +111,7 @@ R3 ...@@ -89,7 +111,7 @@ R3
89 r1 111 r1
90 !s85 0 112 !s85 0
91 31 113 31
92 -R4 114 +R10
93 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 115 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
95 !s101 -O0 117 !s101 -O0
...@@ -103,7 +125,7 @@ R6 ...@@ -103,7 +125,7 @@ R6
103 I9=L>R4ccfGY8^T;U50LY?1 125 I9=L>R4ccfGY8^T;U50LY?1
104 R1 126 R1
105 R2 127 R2
106 -w1591452257 128 +w1592238359
107 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v 129 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
108 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v 130 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
109 L0 1 131 L0 1
...@@ -111,7 +133,7 @@ R3 ...@@ -111,7 +133,7 @@ R3
111 r1 133 r1
112 !s85 0 134 !s85 0
113 31 135 31
114 -Z7 !s108 1591983140.000000 136 +R10
115 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 137 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 138 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
117 !s101 -O0 139 !s101 -O0
...@@ -119,89 +141,111 @@ Z7 !s108 1591983140.000000 ...@@ -119,89 +141,111 @@ Z7 !s108 1591983140.000000
119 R5 141 R5
120 n@data@memory 142 n@data@memory
121 vEX_MEM 143 vEX_MEM
122 -Z8 !s110 1591983141 144 +Z13 !s110 1592304745
123 !i10b 1 145 !i10b 1
124 -!s100 ^^:n;T<R5`c:oReRzT=QT3 146 +!s100 k5Dc_]iZ1_]4AXAj8[5Y<1
125 -IUKd^A=OJc08kD[zWg_`SA2 147 +IeKKdJcFcgGh?YcYVb3j^N0
126 R1 148 R1
127 R2 149 R2
128 -Z9 w1591982553 150 +Z14 w1592266109
129 -Z10 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 151 +Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
130 -Z11 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 152 +Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
131 -L0 149 153 +L0 123
132 R3 154 R3
133 r1 155 r1
134 !s85 0 156 !s85 0
135 31 157 31
136 -Z12 !s108 1591983141.000000 158 +Z17 !s108 1592304745.000000
137 -Z13 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 159 +Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
138 -Z14 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 160 +Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
139 !s101 -O0 161 !s101 -O0
140 !i113 1 162 !i113 1
141 R5 163 R5
142 n@e@x_@m@e@m 164 n@e@x_@m@e@m
143 -vFlush 165 +vHazardHandling
144 R6 166 R6
145 !i10b 1 167 !i10b 1
146 -!s100 G^dZ>]FGe3h^`=G1P?aLA1 168 +!s100 VKUz971>SQ`J8:URRMF9b0
147 -IaJUhT0Va;e^W1QK:FQaQi2 169 +IW^YUaGXi;GJR2jSj4GB9C3
148 R1 170 R1
149 R2 171 R2
150 -Z15 w1591970913 172 +Z20 w1592303944
151 -Z16 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 173 +Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
152 -Z17 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 174 +Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
153 -L0 26 175 +L0 2
154 R3 176 R3
155 r1 177 r1
156 !s85 0 178 !s85 0
157 31 179 31
158 -R7 180 +R10
159 -Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v| 181 +Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
160 -Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v| 182 +Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
161 !s101 -O0 183 !s101 -O0
162 !i113 1 184 !i113 1
163 R5 185 R5
164 -n@flush 186 +n@hazard@handling
165 -vID_EX 187 +vHazardHandling_Forwarding
166 -R8 188 +R6
167 !i10b 1 189 !i10b 1
168 -!s100 ?MgFelQ<oVo:WHdjbIKo00 190 +!s100 `io5UY2OdEBO@7WORJo2m3
169 -ITSSi3aWmi:I7boRWd[i>H3 191 +IgXJLnM0fZLQ69fL0eTX<A3
170 R1 192 R1
171 R2 193 R2
172 -R9 194 +R20
173 -R10 195 +R21
174 -R11 196 +R22
175 -L0 53 197 +L0 58
176 R3 198 R3
177 r1 199 r1
178 !s85 0 200 !s85 0
179 31 201 31
180 -R12 202 +R10
203 +R23
204 +R24
205 +!s101 -O0
206 +!i113 1
207 +R5
208 +n@hazard@handling_@forwarding
209 +vID_EX
181 R13 210 R13
211 +!i10b 1
212 +!s100 H079WzWkDgiK]WV0i2=FW0
213 +IH?JUEX4_FSm8PUM]MkZd41
214 +R1
215 +R2
182 R14 216 R14
217 +R15
218 +R16
219 +L0 56
220 +R3
221 +r1
222 +!s85 0
223 +31
224 +R17
225 +R18
226 +R19
183 !s101 -O0 227 !s101 -O0
184 !i113 1 228 !i113 1
185 R5 229 R5
186 n@i@d_@e@x 230 n@i@d_@e@x
187 vIF_ID 231 vIF_ID
188 -R8 232 +R13
189 !i10b 1 233 !i10b 1
190 -!s100 bEXSIWd8gnI`]GAUe_N>70 234 +!s100 bKKM:?Mi3;B]TOe]O7<e>3
191 -IRmIoA42QB9iZ_NYh`X79>3 235 +I[FaS1INGbXUlELb9411?G2
192 R1 236 R1
193 R2 237 R2
194 -R9 238 +R14
195 -R10 239 +R15
196 -R11 240 +R16
197 -L0 1 241 +L0 27
198 R3 242 R3
199 r1 243 r1
200 !s85 0 244 !s85 0
201 31 245 31
202 -R12 246 +R17
203 -R13 247 +R18
204 -R14 248 +R19
205 !s101 -O0 249 !s101 -O0
206 !i113 1 250 !i113 1
207 R5 251 R5
...@@ -209,11 +253,11 @@ n@i@f_@i@d ...@@ -209,11 +253,11 @@ n@i@f_@i@d
209 vInstructionMemory 253 vInstructionMemory
210 R6 254 R6
211 !i10b 1 255 !i10b 1
212 -!s100 dUP:<mGld?9A^?GbR`HX41 256 +!s100 cSI5j20TebFBX<a8i4YC;1
213 -Ijoe6hdS43:Kg7S<nf[6_S3 257 +ILAL:4@oQ@4VF>=@T80I7=2
214 R1 258 R1
215 R2 259 R2
216 -w1591979413 260 +w1592295803
217 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 261 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
218 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
219 L0 1 263 L0 1
...@@ -221,7 +265,7 @@ R3 ...@@ -221,7 +265,7 @@ R3
221 r1 265 r1
222 !s85 0 266 !s85 0
223 31 267 31
224 -R7 268 +R10
225 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
226 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
227 !s101 -O0 271 !s101 -O0
...@@ -229,57 +273,79 @@ R7 ...@@ -229,57 +273,79 @@ R7
229 R5 273 R5
230 n@instruction@memory 274 n@instruction@memory
231 vMEM_WB 275 vMEM_WB
232 -R8 276 +R13
233 !i10b 1 277 !i10b 1
234 -!s100 9m=P24TTjNA?g>P@e6;[=2 278 +!s100 FbXVboThZG;k@R0iW>;8`1
235 -I3VBN<k:`mX_jIkFWMoi3a2 279 +ITAUac1`E05Wn30@dIl3i`0
236 R1 280 R1
237 R2 281 R2
238 -R9 282 +R14
239 -R10 283 +R15
240 -R11 284 +R16
241 -L0 181 285 +L0 172
242 R3 286 R3
243 r1 287 r1
244 !s85 0 288 !s85 0
245 31 289 31
246 -R12 290 +R17
247 -R13 291 +R18
248 -R14 292 +R19
249 !s101 -O0 293 !s101 -O0
250 !i113 1 294 !i113 1
251 R5 295 R5
252 n@m@e@m_@w@b 296 n@m@e@m_@w@b
253 vMIPS_Pipeline 297 vMIPS_Pipeline
254 -R6 298 +R13
255 !i10b 1 299 !i10b 1
256 -!s100 AkG9Fhg`zlP55C:McA:FM2 300 +!s100 =ha3Og:JFS8E9e9EGH_R^3
257 -IZRIYdAdZBSFN3o<CV_WgK0 301 +I5MH@bIHF6WJ7WY5bK7;723
258 R1 302 R1
259 R2 303 R2
260 -w1591980998 304 +w1592293934
261 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 305 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 306 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
263 -L0 2 307 +L0 1
264 R3 308 R3
265 r1 309 r1
266 !s85 0 310 !s85 0
267 31 311 31
268 -R7 312 +R10
269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 313 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 314 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
271 !s101 -O0 315 !s101 -O0
272 !i113 1 316 !i113 1
273 R5 317 R5
274 n@m@i@p@s_@pipeline 318 n@m@i@p@s_@pipeline
319 +vMIPS_Pipeline_Forwarding
320 +R13
321 +!i10b 1
322 +!s100 0[k6421_Q:5fJX9:k0cCE0
323 +I3WHKNdD6XohmDV_eiT8^c1
324 +R1
325 +R2
326 +w1592303982
327 +8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
328 +FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
329 +L0 2
330 +R3
331 +r1
332 +!s85 0
333 +31
334 +R17
335 +!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
336 +!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
337 +!s101 -O0
338 +!i113 1
339 +R5
340 +n@m@i@p@s_@pipeline_@forwarding
275 vMIPS_SingleCycle 341 vMIPS_SingleCycle
276 -R8 342 +R13
277 !i10b 1 343 !i10b 1
278 -!s100 ;_UzWlV_FikM_gED@zTjP2 344 +!s100 gM[;Cl]DhJhX67JceN9VX0
279 -IQEAV;clN[65lKfZREk<=Q1 345 +IEZ2gnb65W:EYTLgmRHR8f2
280 R1 346 R1
281 R2 347 R2
282 -w1591976493 348 +w1592102255
283 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 349 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
284 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 350 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
285 L0 1 351 L0 1
...@@ -287,7 +353,7 @@ R3 ...@@ -287,7 +353,7 @@ R3
287 r1 353 r1
288 !s85 0 354 !s85 0
289 31 355 31
290 -R7 356 +R17
291 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 357 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
292 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 358 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
293 !s101 -O0 359 !s101 -O0
...@@ -295,101 +361,123 @@ R7 ...@@ -295,101 +361,123 @@ R7
295 R5 361 R5
296 n@m@i@p@s_@single@cycle 362 n@m@i@p@s_@single@cycle
297 vMux32bit 363 vMux32bit
298 -R8 364 +R13
299 !i10b 1 365 !i10b 1
300 !s100 foJG^YU75_eND1Og;6Z>O1 366 !s100 foJG^YU75_eND1Og;6Z>O1
301 II3=gjhQD0_cn8mlDL]@bi1 367 II3=gjhQD0_cn8mlDL]@bi1
302 R1 368 R1
303 R2 369 R2
304 -Z20 w1591452448 370 +Z25 w1591452448
305 -Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 371 +Z26 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
306 -Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 372 +Z27 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
307 L0 15 373 L0 15
308 R3 374 R3
309 r1 375 r1
310 !s85 0 376 !s85 0
311 31 377 31
312 -R12 378 +R17
313 -Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 379 +Z28 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
314 -Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 380 +Z29 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
315 !s101 -O0 381 !s101 -O0
316 !i113 1 382 !i113 1
317 R5 383 R5
318 n@mux32bit 384 n@mux32bit
319 vMux5bit 385 vMux5bit
320 -R8 386 +R13
321 !i10b 1 387 !i10b 1
322 !s100 oSd=[kHDJb<:G7LN4]6@e3 388 !s100 oSd=[kHDJb<:G7LN4]6@e3
323 IfiVXg_aB2GQG7?F@=HcEi0 389 IfiVXg_aB2GQG7?F@=HcEi0
324 R1 390 R1
325 R2 391 R2
392 +R25
393 +R26
394 +R27
395 +L0 1
396 +R3
397 +r1
398 +!s85 0
399 +31
400 +R17
401 +R28
402 +R29
403 +!s101 -O0
404 +!i113 1
405 +R5
406 +n@mux5bit
407 +vMux_Forwarding
408 +R6
409 +!i10b 1
410 +!s100 85b4ZkTg28cdHOcJHT1i<1
411 +Ii2ZN`=VNWde5:dd4gJ:@_3
412 +R1
413 +R2
326 R20 414 R20
327 R21 415 R21
328 R22 416 R22
329 -L0 1 417 +L0 124
330 R3 418 R3
331 r1 419 r1
332 !s85 0 420 !s85 0
333 31 421 31
334 -R12 422 +R10
335 R23 423 R23
336 R24 424 R24
337 !s101 -O0 425 !s101 -O0
338 !i113 1 426 !i113 1
339 R5 427 R5
340 -n@mux5bit 428 +n@mux_@forwarding
341 vMuxBranchSignal 429 vMuxBranchSignal
342 -R8 430 +R13
343 !i10b 1 431 !i10b 1
344 !s100 H1RKS9h`Y6QFX88CRc<g[0 432 !s100 H1RKS9h`Y6QFX88CRc<g[0
345 IGJT?gXMKEEWH?G^lPN79V2 433 IGJT?gXMKEEWH?G^lPN79V2
346 R1 434 R1
347 R2 435 R2
348 -R20 436 +R25
349 -R21 437 +R26
350 -R22 438 +R27
351 L0 29 439 L0 29
352 R3 440 R3
353 r1 441 r1
354 !s85 0 442 !s85 0
355 31 443 31
356 -R12 444 +R17
357 -R23 445 +R28
358 -R24 446 +R29
359 !s101 -O0 447 !s101 -O0
360 !i113 1 448 !i113 1
361 R5 449 R5
362 n@mux@branch@signal 450 n@mux@branch@signal
363 -vPCcounter 451 +vPCregister
364 -R8 452 +R13
365 !i10b 1 453 !i10b 1
366 -!s100 WeKa=V6mT9ZlU8@mTC`g42 454 +!s100 ZWKU[XiaKQUFo0lg:i>8J3
367 -Il_T>dO3a82KCcjIcT0_8<0 455 +IJN5hl<_id]kA5B6k4:9oE1
368 R1 456 R1
369 R2 457 R2
370 -R9 458 +R14
371 -R10 459 +R15
372 -R11 460 +R16
373 -L0 208 461 +L0 1
374 R3 462 R3
375 r1 463 r1
376 !s85 0 464 !s85 0
377 31 465 31
378 -R12 466 +R17
379 -R13 467 +R18
380 -R14 468 +R19
381 !s101 -O0 469 !s101 -O0
382 !i113 1 470 !i113 1
383 R5 471 R5
384 -n@p@ccounter 472 +n@p@cregister
385 vRegister 473 vRegister
386 -R8 474 +R13
387 !i10b 1 475 !i10b 1
388 !s100 bC`<7GaPg=bDaZoUR<ADa0 476 !s100 bC`<7GaPg=bDaZoUR<ADa0
389 I<aR5RJ2c1Qba>GdC]KZCd2 477 I<aR5RJ2c1Qba>GdC]KZCd2
390 R1 478 R1
391 R2 479 R2
392 -w1591452599 480 +w1592238349
393 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 481 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
394 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 482 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
395 L0 1 483 L0 1
...@@ -397,7 +485,7 @@ R3 ...@@ -397,7 +485,7 @@ R3
397 r1 485 r1
398 !s85 0 486 !s85 0
399 31 487 31
400 -R12 488 +R17
401 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 489 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
402 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 490 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
403 !s101 -O0 491 !s101 -O0
...@@ -405,7 +493,7 @@ R12 ...@@ -405,7 +493,7 @@ R12
405 R5 493 R5
406 n@register 494 n@register
407 vShiftLeft2 495 vShiftLeft2
408 -R8 496 +!s110 1592304746
409 !i10b 1 497 !i10b 1
410 !s100 ]Zje9D[f?jFRnJBn`OeHc1 498 !s100 ]Zje9D[f?jFRnJBn`OeHc1
411 I]0TYJ]_7?FkOoY=2GlT5=3 499 I]0TYJ]_7?FkOoY=2GlT5=3
...@@ -419,7 +507,7 @@ R3 ...@@ -419,7 +507,7 @@ R3
419 r1 507 r1
420 !s85 0 508 !s85 0
421 31 509 31
422 -R12 510 +R17
423 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 511 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
424 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 512 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
425 !s101 -O0 513 !s101 -O0
...@@ -448,25 +536,3 @@ R4 ...@@ -448,25 +536,3 @@ R4
448 !i113 1 536 !i113 1
449 R5 537 R5
450 n@sign@extend 538 n@sign@extend
451 -vStall
452 -R6
453 -!i10b 1
454 -!s100 z^N=>UeP;k2mNYmKnG`WR2
455 -IOg[[<<GgT4k[<hhzADXMC3
456 -R1
457 -R2
458 -R15
459 -R16
460 -R17
461 -L0 2
462 -R3
463 -r1
464 -!s85 0
465 -31
466 -R7
467 -R18
468 -R19
469 -!s101 -O0
470 -!i113 1
471 -R5
472 -n@stall
......
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