2020-1-capstone-design1 / KNW_Project2

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Showing 13 changed files with 108 additions and 69 deletions
......@@ -2,10 +2,11 @@
module HazardHandling(clk,
in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, // for data hazard handling
in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, // for control hazard handling
in_id_jump, in_id_branch, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, // for control hazard handling
out_stallsignal, out_flushsignal, out_nextPC);
input clk;
input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch;
input[2:0] in_id_branch;
input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
input[31:0] in_wb_nextPC;
......@@ -13,15 +14,48 @@ output reg out_stallsignal;
output reg[4:0] out_flushsignal;
output reg[31:0] out_nextPC;
reg isbranch;
reg[4:0] readreg2;
initial begin
isbranch = 1'b0;
readreg2 <= 5'b00000;
out_stallsignal <= 1'b0;
out_flushsignal <= 5'b00000;
out_nextPC <= 32'h00000000;
end
always @(negedge clk) begin
if(isbranch == 1'b1 && in_ex_branch == 1'b1) begin
out_flushsignal = 5'b11100;
isbranch = 1'b0;
end else begin
isbranch = 1'b0;
// Data Hazard Handling
readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else begin
out_stallsignal = 1'b0;
// Control Hazard Handling
if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
else if(in_id_branch != 3'b000) isbranch = 1'b1;
else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
out_nextPC = in_wb_nextPC;
out_flushsignal[4] = 1'b0;
end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
end
end
end
/*
always @(negedge clk) begin
// Data Hazard Handling
readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
......@@ -45,6 +79,7 @@ always @(negedge clk) begin
end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
end
end
*/
endmodule
......
......@@ -4,51 +4,55 @@ input[31:0] address;
output reg[31:0] instruction;
reg[31:0] instr_mem[127:0];
/*
initial begin
end
*/
/*
// Factorial #1
initial begin
instr_mem[0] = 32'd0;
instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[3] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
instr_mem[4] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[5] = 32'd0;
instr_mem[6] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
instr_mem[7] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[8] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[9] = 32'd0;
instr_mem[10] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
instr_mem[11] = 32'b00100100000010010000000000000001; // addi, $0 $9 1
instr_mem[12] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
instr_mem[13] = 32'd0;
instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
instr_mem[1] = 32'b00100000000010000000000000001010; // addi, $0, $t0($8), +10
instr_mem[2] = 32'b00100001001010010000000000000001; // addi, $t1($9), $t1($9), +1
instr_mem[3] = 32'b00000010000010010000000000011000; // mult, $s0($16), $t1($9)
instr_mem[4] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[5] = 32'b00010101000010011111111111111100; // bne, $t0($8), $t1($9), -4
instr_mem[6] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0
end
*/
/*
// Factorial #2
initial begin
instr_mem[0] = 32'b00100111000110000000000111111111; // addi, $24 $24 511
instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9
instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10
instr_mem[5] = 32'b00010001000010100000000000000101; // beq, $8 $10 +5
instr_mem[6] = 32'b00000001000010010000000000011000; // mult, $8 $9
instr_mem[7] = 32'b00000001000000000111100000100000; // add, $8 $0 $15
instr_mem[8] = 32'd0;
instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12
instr_mem[10] = 32'b00000000000000000110100000010010; // mflo, $13
instr_mem[11] = 32'b10101100000010010000000000111100; // sw, $0 $9 60
instr_mem[12] = 32'd0;
instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
instr_mem[15] = 32'b00001100000000000000000000010001; // jal, 17
instr_mem[16] = 32'b00000001000010010000000000011000; // mult, $8 $9
instr_mem[17] = 32'b00000000000000000000000000001000; // jr, $0
instr_mem[18] = 32'b00000001000010010000000000011000; // mult, $8 $9
instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
instr_mem[1] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[2] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[3] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[4] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[5] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[6] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[7] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[8] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[9] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[10] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[11] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[12] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[13] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[14] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[15] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[16] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[17] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[18] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[19] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[20] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[21] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[22] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[23] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[24] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[25] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[26] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[27] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[28] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
instr_mem[29] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
instr_mem[30] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[31] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0
end
*/
always @ (*) begin
instruction = instr_mem[address/4];
......
D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Adder
-- Compiling module MIPS_Pipeline_Forwarding
Top level modules:
Adder
MIPS_Pipeline_Forwarding
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module MIPS_Pipeline_Forwarding
-- Compiling module Adder
Top level modules:
MIPS_Pipeline_Forwarding
Adder
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......@@ -33,6 +33,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
Top level modules:
Register
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module MIPS_Pipeline
Top level modules:
MIPS_Pipeline
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module PCregister
......@@ -48,13 +55,6 @@ Top level modules:
EX_MEM
MEM_WB
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module MIPS_Pipeline
Top level modules:
MIPS_Pipeline
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module HazardHandling
......@@ -66,13 +66,6 @@ Top level modules:
HazardHandling_Forwarding
Mux_Forwarding
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module SignExtend
Top level modules:
SignExtend
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Control
......@@ -80,12 +73,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
Top level modules:
Control
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ALU
-- Compiling module SignExtend
Top level modules:
ALU
SignExtend
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......@@ -98,12 +91,12 @@ Top level modules:
Mux32bit
MuxBranchSignal
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ShiftLeft2
-- Compiling module ALU
Top level modules:
ShiftLeft2
ALU
} {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......@@ -112,7 +105,14 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
Top level modules:
DataMemory
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ShiftLeft2
Top level modules:
ShiftLeft2
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Clock
-- Compiling module Clock_pipeline
......
This diff is collapsed. Click to expand it.
......@@ -55,7 +55,7 @@ PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
HazardHandling hazardhandling(clk,
ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, // for data hazard handling
ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,
ctrl_jump, branch_signal, memwb_jump, memwb_branch, nextPC,
ctrl_jump, ctrl_branch, branch_signal, memwb_jump, memwb_branch, nextPC,
stallsignal, flushsignal, flush_nextPC);
// Instruction Fetch
......
......@@ -12,6 +12,6 @@ module Clock_pipeline(clk);
output reg clk;
initial clk = 0;
always #11 clk = ~clk;
always #10 clk = ~clk;
endmodule
......
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