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Commit 19cd8e0215686fe2a886808c301e918c03f5320c 19cd8e02 1 parent 30c9af9d
Showing 13 changed files with 306 additions and 267 deletions
Project/MIPS/HazardHandling.v
Project/MIPS/InstructionMemory.v
Project/MIPS/MIPS_CPU.cr.mti
Project/MIPS/MIPS_CPU.mpf
Project/MIPS/MIPS_Pipeline.v
Project/MIPS/clock.v
Project/MIPS/vsim.wlf
Project/MIPS/work/_info
Project/MIPS/work/_lib.qdb
Project/MIPS/work/_lib1_0.qdb
Project/MIPS/work/_lib1_3.qdb
Project/MIPS/work/_lib1_0.qpg → Project/MIPS/work/_lib1_3.qpg
Project/MIPS/work/_lib1_0.qtl → Project/MIPS/work/_lib1_3.qtl
--- a/Project/MIPS/HazardHandling.v
View file @19cd8e0
+++ b/Project/MIPS/HazardHandling.v
View file @19cd8e0
@@ -2,10 +2,11 @@
 module HazardHandling(clk, 
 	in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 									// for data hazard handling
 	in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 						
- 	in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, 										// for control hazard handling
+ 	in_id_jump, in_id_branch, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, 										// for control hazard handling
 	out_stallsignal, out_flushsignal, out_nextPC);
 input clk;
 input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch;
+ input[2:0] in_id_branch;
 input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
 input[31:0] in_wb_nextPC;
 
@@ -13,15 +14,48 @@ output reg out_stallsignal;
 output reg[4:0] out_flushsignal;
 output reg[31:0] out_nextPC;
 
+ reg isbranch;
 reg[4:0] readreg2;
 
 initial begin
+ 	isbranch = 1'b0;
 	readreg2 <= 5'b00000;
 	out_stallsignal <= 1'b0;
 	out_flushsignal <= 5'b00000;
 	out_nextPC <= 32'h00000000;
 end
 always @(negedge clk) begin
+ 	if(isbranch == 1'b1 && in_ex_branch == 1'b1) begin
+ 		out_flushsignal = 5'b11100;
+ 		isbranch = 1'b0;
+ 	end else begin
+ 		isbranch = 1'b0;
+ // Data Hazard Handling
+ 		readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
+ 		if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
+ 			out_stallsignal = 1'b1;
+ 			out_flushsignal = 5'b00100;
+ 		end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
+ 			out_stallsignal = 1'b1;
+ 			out_flushsignal = 5'b00100;
+ 		end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
+ 			out_stallsignal = 1'b1;	
+ 			out_flushsignal = 5'b00100;
+ 		end else begin
+ 			out_stallsignal = 1'b0;
+ 
+ // Control Hazard Handling
+ 			if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
+ 			else if(in_id_branch != 3'b000) isbranch = 1'b1;
+ 			else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
+ 				out_nextPC = in_wb_nextPC;
+ 				out_flushsignal[4] = 1'b0;
+ 			end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
+ 		end
+ 	end
+ end
+ /*
+ always @(negedge clk) begin
 // Data Hazard Handling
 	readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
 	if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
@@ -45,6 +79,7 @@ always @(negedge clk) begin
 		end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
 	end
 end
+ */
 endmodule
 
 
--- a/Project/MIPS/InstructionMemory.v
View file @19cd8e0
+++ b/Project/MIPS/InstructionMemory.v
View file @19cd8e0
@@ -4,51 +4,55 @@ input[31:0] address;
 output reg[31:0] instruction;
 
 reg[31:0] instr_mem[127:0];
- /*
- initial begin
 
- end
- */
- /*
+ // Factorial #1
 initial begin
- instr_mem[0] = 32'd0;
- instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[3] = 32'b00100101101011010000000000000011;		// addi, $13 $13 3
- instr_mem[4] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[5] = 32'd0;
- instr_mem[6] = 32'b00100101101011010000000000000011;		// addi, $13 $13 3
- instr_mem[7] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[8] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[9] = 32'd0;
- instr_mem[10] = 32'b00100101101011010000000000000011;		// addi, $13 $13 3
- instr_mem[11] = 32'b00100100000010010000000000000001;		// addi, $0 $9 1
- instr_mem[12] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
- instr_mem[13] = 32'd0;
+ instr_mem[0] = 32'b00100000000100000000000000000001;		// addi, $0, $s0($16), +1
+ instr_mem[1] = 32'b00100000000010000000000000001010;		// addi, $0, $t0($8), +10
+ instr_mem[2] = 32'b00100001001010010000000000000001;		// addi, $t1($9), $t1($9), +1
+ instr_mem[3] = 32'b00000010000010010000000000011000;		// mult, $s0($16), $t1($9)
+ instr_mem[4] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[5] = 32'b00010101000010011111111111111100;		// bne, $t0($8), $t1($9), -4
+ instr_mem[6] = 32'b00100010000000100000000000000000;		// addi, $s0($16), $v0($2), +0
 end
- */
 
+ /*
+ // Factorial #2
 initial begin
- instr_mem[0] = 32'b00100111000110000000000111111111;		// addi, $24 $24 511
- instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
- instr_mem[3] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
- instr_mem[4] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
- instr_mem[5] = 32'b00010001000010100000000000000101;		// beq, $8 $10 +5
- instr_mem[6] = 32'b00000001000010010000000000011000;		// mult, $8 $9
- instr_mem[7] = 32'b00000001000000000111100000100000;		// add, $8 $0 $15
- instr_mem[8] = 32'd0;
- instr_mem[9] = 32'b00000000000000000110000000010000;		// mfhi, $12
- instr_mem[10] = 32'b00000000000000000110100000010010;		// mflo, $13
- instr_mem[11] = 32'b10101100000010010000000000111100;		// sw, $0 $9 60
- instr_mem[12] = 32'd0;
- instr_mem[13] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
- instr_mem[14] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
- instr_mem[15] = 32'b00001100000000000000000000010001;		// jal, 17
- instr_mem[16] = 32'b00000001000010010000000000011000;		// mult, $8 $9
- instr_mem[17] = 32'b00000000000000000000000000001000;		// jr, $0
- instr_mem[18] = 32'b00000001000010010000000000011000;		// mult, $8 $9
+ instr_mem[0] = 32'b00100000000100000000000000000001;		// addi, $0, $s0($16), +1
+ instr_mem[1] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[2] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[3] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[4] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[5] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[6] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[7] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[8] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[9] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[10] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[11] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[12] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[13] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[14] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[15] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[16] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[17] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[18] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[19] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[20] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[21] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[22] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[23] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[24] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[25] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[26] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[27] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[28] = 32'b00100001000010000000000000000001;		// addi, $t0($8), $t0($8), +1
+ instr_mem[29] = 32'b00000010000010000000000000011000;		// mult, $s0($16), $t0($8)
+ instr_mem[30] = 32'b00000000000000001000000000010010;		// mflo, $s0($16)
+ instr_mem[31] = 32'b00100010000000100000000000000000;		// addi, $s0($16), $v0($2), +0
 end
+ */
 
 always @ (*) begin
 	instruction = instr_mem[address/4];
--- a/Project/MIPS/MIPS_CPU.cr.mti
View file @19cd8e0
+++ b/Project/MIPS/MIPS_CPU.cr.mti
View file @19cd8e0
- D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
+ D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
- -- Compiling module Adder
+ -- Compiling module MIPS_Pipeline_Forwarding
 
 Top level modules:
- 	Adder
+ 	MIPS_Pipeline_Forwarding
 
- } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
+ } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
- -- Compiling module MIPS_Pipeline_Forwarding
+ -- Compiling module Adder
 
 Top level modules:
- 	MIPS_Pipeline_Forwarding
+ 	Adder
 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
@@ -33,6 +33,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 
 Top level modules:
 	Register
 
+ } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+ -- Compiling module MIPS_Pipeline
+ 
+ Top level modules:
+ 	MIPS_Pipeline
+ 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module PCregister
@@ -48,13 +55,6 @@ Top level modules:
 	EX_MEM
 	MEM_WB
 
- } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
- Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
- -- Compiling module MIPS_Pipeline
- 
- Top level modules:
- 	MIPS_Pipeline
- 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module HazardHandling
@@ -66,13 +66,6 @@ Top level modules:
 	HazardHandling_Forwarding
 	Mux_Forwarding
 
- } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
- Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
- -- Compiling module SignExtend
- 
- Top level modules:
- 	SignExtend
- 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Control
@@ -80,12 +73,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 
 Top level modules:
 	Control
 
- } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+ } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
- -- Compiling module ALU
+ -- Compiling module SignExtend
 
 Top level modules:
- 	ALU
+ 	SignExtend
 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
@@ -98,12 +91,12 @@ Top level modules:
 	Mux32bit
 	MuxBranchSignal
 
- } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+ } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
- -- Compiling module ShiftLeft2
+ -- Compiling module ALU
 
 Top level modules:
- 	ShiftLeft2
+ 	ALU
 
 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
@@ -112,7 +105,14 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 
 Top level modules:
 	DataMemory
 
- } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+ } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+ -- Compiling module ShiftLeft2
+ 
+ Top level modules:
+ 	ShiftLeft2
+ 
+ } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Clock
 -- Compiling module Clock_pipeline
--- a/Project/MIPS/MIPS_CPU.mpf
View file @19cd8e0
+++ b/Project/MIPS/MIPS_CPU.mpf
View file @19cd8e0
@@ -816,7 +816,7 @@ Resolution = ns
 UserTimeUnit = default
 
 ; Default run length
- RunLength = 100
+ RunLength = 100 ns
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 10000000
@@ -2036,35 +2036,35 @@ Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 15
 Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
- Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039528 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
- Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592303982 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1592320265 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
- Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592102255 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
- Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592295803 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1592357286 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
- Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238349 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
- Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592266109 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
- Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592293934 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1592319215 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
- Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592303944 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1592320280 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
- Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039196 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
- Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592280009 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
- Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238365 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
- Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452448 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
- Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039219 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
- Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238359 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
- Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592091089 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
+ Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1592320589 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
--- a/Project/MIPS/MIPS_Pipeline.v
View file @19cd8e0
+++ b/Project/MIPS/MIPS_Pipeline.v
View file @19cd8e0
@@ -55,7 +55,7 @@ PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
 HazardHandling hazardhandling(clk, 
 	ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, 				// for data hazard handling
 	ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, 
- 	ctrl_jump, branch_signal, memwb_jump, memwb_branch, nextPC, 
+ 	ctrl_jump, ctrl_branch, branch_signal, memwb_jump, memwb_branch, nextPC, 
 	stallsignal, flushsignal, flush_nextPC);
 
 // Instruction Fetch
--- a/Project/MIPS/clock.v
View file @19cd8e0
+++ b/Project/MIPS/clock.v
View file @19cd8e0
@@ -12,6 +12,6 @@ module Clock_pipeline(clk);
 output reg clk;
 
 initial clk = 0;
- always #11 clk = ~clk;
+ always #10 clk = ~clk;
 endmodule
 
--- a/Project/MIPS/vsim.wlf 0 → 100644
View file @19cd8e0
+++ b/Project/MIPS/vsim.wlf 0 → 100644
View file @19cd8e0
--- a/Project/MIPS/work/_info
View file @19cd8e0
+++ b/Project/MIPS/work/_info
View file @19cd8e0
@@ -9,510 +9,510 @@ z2
 cModel Technology
 dC:/Modeltech_pe_edu_10.4a/examples
 vAdder
- Z0 !s110 1592304743
+ Z0 !s110 1592320284
 !i10b 1
 !s100 LKl?GBS:oo[A[hLP0Qb^_1
 IlbJEP?2C3Ya>zhzD12^S]1
 Z1 VDg1SIo80bB@j0V0VzS_@n1
 Z2 dD:/class/Capstone1/KNW_Project2/Project/MIPS
- w1591039528
+ Z3 w1592318418
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 L0 1
- Z3 OP;L;10.4a;61
+ Z4 OP;L;10.4a;61
 r1
 !s85 0
 31
- Z4 !s108 1592304743.000000
+ Z5 !s108 1592320284.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s101 -O0
 !i113 1
- Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
+ Z6 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
 n@adder
 vALU
- Z6 !s110 1592304744
+ R0
 !i10b 1
 !s100 z[hZ0^@Q34FnkzY3g0ioc2
 ImZ3]6XT73YVLGl?0_=9k33
 R1
 R2
- w1592238365
+ R3
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R4
+ R5
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@a@l@u
 vClock
- R6
+ Z7 !s110 1592320593
 !i10b 1
 !s100 i65lY=7B8[4>bmAoJ2kDB2
- I0GMR?JQ97PaC17BI<HeS82
+ IA2Ge3:5`hDcK4mi0FDSL[3
 R1
 R2
- Z7 w1592091089
- Z8 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
- Z9 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+ Z8 w1592320589
+ Z9 8D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
+ Z10 FD:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- Z10 !s108 1592304744.000000
- Z11 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
- Z12 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
+ Z11 !s108 1592320593.000000
+ Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
+ Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@clock
 vClock_pipeline
- R6
+ R7
 !i10b 1
- !s100 dPQB6MR4Y;CLL9a@O1o1B0
- I7@GBo9UQ711@mL4ZBf;@Z1
+ !s100 =@aPTZQSFah27j5MeG_d62
+ I8]3=4M<>=TGn3hX;LeQ183
 R1
 R2
- R7
 R8
 R9
+ R10
 L0 10
- R3
+ R4
 r1
 !s85 0
 31
- R10
 R11
 R12
+ R13
 !s101 -O0
 !i113 1
- R5
+ R6
 n@clock_pipeline
 vControl
- R6
+ Z14 !s110 1592320285
 !i10b 1
 !s100 PKg@cjO2lUjfUI`iaE9QB2
 IX2Ii?h^g2a@DaCi9:L8BU1
 R1
 R2
- w1592280009
+ R3
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R10
+ Z15 !s108 1592320285.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@control
 vDataMemory
- R6
+ R14
 !i10b 1
 !s100 e=5E[GS05J<RCdT=KSMX_1
 I9=L>R4ccfGY8^T;U50LY?1
 R1
 R2
- w1592238359
+ R3
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R10
+ R15
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@data@memory
 vEX_MEM
- Z13 !s110 1592304745
+ Z16 !s110 1592320286
 !i10b 1
 !s100 k5Dc_]iZ1_]4AXAj8[5Y<1
 IeKKdJcFcgGh?YcYVb3j^N0
 R1
 R2
- Z14 w1592266109
- Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
- Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+ Z17 w1592318419
+ Z18 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+ Z19 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
 L0 123
- R3
+ R4
 r1
 !s85 0
 31
- Z17 !s108 1592304745.000000
- Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
- Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+ Z20 !s108 1592320286.000000
+ Z21 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+ Z22 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@e@x_@m@e@m
 vHazardHandling
- R6
+ R14
 !i10b 1
- !s100 VKUz971>SQ`J8:URRMF9b0
- IW^YUaGXi;GJR2jSj4GB9C3
+ !s100 c>lJVMk@fzVaBjU0aV@h51
+ I:QLSJeiP@1NnaB^lRd6_l2
 R1
 R2
- Z20 w1592303944
- Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
- Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+ Z23 w1592320280
+ Z24 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+ Z25 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
 L0 2
- R3
+ R4
 r1
 !s85 0
 31
- R10
- Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
- Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+ R15
+ Z26 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+ Z27 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@hazard@handling
 vHazardHandling_Forwarding
- R6
+ R14
 !i10b 1
- !s100 `io5UY2OdEBO@7WORJo2m3
- IgXJLnM0fZLQ69fL0eTX<A3
+ !s100 7f=OHLAZQeViCagN[c9Sf3
+ IZ44zQQI;2gGiN8L`RbQ<=1
 R1
 R2
- R20
- R21
- R22
- L0 58
- R3
+ R23
+ R24
+ R25
+ L0 93
+ R4
 r1
 !s85 0
 31
- R10
- R23
- R24
+ R15
+ R26
+ R27
 !s101 -O0
 !i113 1
- R5
+ R6
 n@hazard@handling_@forwarding
 vID_EX
- R13
+ R16
 !i10b 1
 !s100 H079WzWkDgiK]WV0i2=FW0
 IH?JUEX4_FSm8PUM]MkZd41
 R1
 R2
- R14
- R15
- R16
+ R17
+ R18
+ R19
 L0 56
- R3
+ R4
 r1
 !s85 0
 31
- R17
- R18
- R19
+ R20
+ R21
+ R22
 !s101 -O0
 !i113 1
- R5
+ R6
 n@i@d_@e@x
 vIF_ID
- R13
+ R16
 !i10b 1
 !s100 bKKM:?Mi3;B]TOe]O7<e>3
 I[FaS1INGbXUlELb9411?G2
 R1
 R2
- R14
- R15
- R16
+ R17
+ R18
+ R19
 L0 27
- R3
+ R4
 r1
 !s85 0
 31
- R17
- R18
- R19
+ R20
+ R21
+ R22
 !s101 -O0
 !i113 1
- R5
+ R6
 n@i@f_@i@d
 vInstructionMemory
- R6
+ !s110 1592357290
 !i10b 1
- !s100 cSI5j20TebFBX<a8i4YC;1
- ILAL:4@oQ@4VF>=@T80I7=2
+ !s100 5C;cU;MQ6jR<THFX]C[C_0
+ IYmf<mb=ca6ZWglS@o9l@c0
 R1
 R2
- w1592295803
+ w1592357286
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R10
+ !s108 1592357290.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@instruction@memory
 vMEM_WB
- R13
+ R16
 !i10b 1
 !s100 FbXVboThZG;k@R0iW>;8`1
 ITAUac1`E05Wn30@dIl3i`0
 R1
 R2
- R14
- R15
- R16
+ R17
+ R18
+ R19
 L0 172
- R3
+ R4
 r1
 !s85 0
 31
- R17
- R18
- R19
+ R20
+ R21
+ R22
 !s101 -O0
 !i113 1
- R5
+ R6
 n@m@e@m_@w@b
 vMIPS_Pipeline
- R13
+ R16
 !i10b 1
- !s100 =ha3Og:JFS8E9e9EGH_R^3
- I5MH@bIHF6WJ7WY5bK7;723
+ !s100 =YiG<BP8;FThR9<Of:]<42
+ Iz:PlBdl:5iijJ8LoFBAOe1
 R1
 R2
- w1592293934
+ w1592319215
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R10
+ R15
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@m@i@p@s_@pipeline
 vMIPS_Pipeline_Forwarding
- R13
+ R16
 !i10b 1
 !s100 0[k6421_Q:5fJX9:k0cCE0
 I3WHKNdD6XohmDV_eiT8^c1
 R1
 R2
- w1592303982
+ w1592320265
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
 L0 2
- R3
+ R4
 r1
 !s85 0
 31
- R17
+ R20
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@m@i@p@s_@pipeline_@forwarding
 vMIPS_SingleCycle
- R13
+ R16
 !i10b 1
 !s100 gM[;Cl]DhJhX67JceN9VX0
 IEZ2gnb65W:EYTLgmRHR8f2
 R1
 R2
- w1592102255
+ R3
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R17
+ R20
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@m@i@p@s_@single@cycle
 vMux32bit
- R13
+ R16
 !i10b 1
 !s100 foJG^YU75_eND1Og;6Z>O1
 II3=gjhQD0_cn8mlDL]@bi1
 R1
 R2
- Z25 w1591452448
- Z26 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
- Z27 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+ R17
+ Z28 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+ Z29 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
 L0 15
- R3
+ R4
 r1
 !s85 0
 31
- R17
- Z28 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
- Z29 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+ R20
+ Z30 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+ Z31 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@mux32bit
 vMux5bit
- R13
+ R16
 !i10b 1
 !s100 oSd=[kHDJb<:G7LN4]6@e3
 IfiVXg_aB2GQG7?F@=HcEi0
 R1
 R2
- R25
- R26
- R27
+ R17
+ R28
+ R29
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R17
- R28
- R29
+ R20
+ R30
+ R31
 !s101 -O0
 !i113 1
- R5
+ R6
 n@mux5bit
 vMux_Forwarding
- R6
+ R14
 !i10b 1
- !s100 85b4ZkTg28cdHOcJHT1i<1
- Ii2ZN`=VNWde5:dd4gJ:@_3
+ !s100 iCag5di1L;N5IB81hdLH>2
+ I:XNmLIF]Ed49A_PQCSjO=0
 R1
 R2
- R20
- R21
- R22
- L0 124
- R3
+ R23
+ R24
+ R25
+ L0 159
+ R4
 r1
 !s85 0
 31
- R10
- R23
- R24
+ R15
+ R26
+ R27
 !s101 -O0
 !i113 1
- R5
+ R6
 n@mux_@forwarding
 vMuxBranchSignal
- R13
+ R16
 !i10b 1
 !s100 H1RKS9h`Y6QFX88CRc<g[0
 IGJT?gXMKEEWH?G^lPN79V2
 R1
 R2
- R25
- R26
- R27
+ R17
+ R28
+ R29
 L0 29
- R3
+ R4
 r1
 !s85 0
 31
- R17
- R28
- R29
+ R20
+ R30
+ R31
 !s101 -O0
 !i113 1
- R5
+ R6
 n@mux@branch@signal
 vPCregister
- R13
+ R16
 !i10b 1
 !s100 ZWKU[XiaKQUFo0lg:i>8J3
 IJN5hl<_id]kA5B6k4:9oE1
 R1
 R2
- R14
- R15
- R16
+ R17
+ R18
+ R19
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R17
- R18
- R19
+ R20
+ R21
+ R22
 !s101 -O0
 !i113 1
- R5
+ R6
 n@p@cregister
 vRegister
- R13
+ Z32 !s110 1592320287
 !i10b 1
 !s100 bC`<7GaPg=bDaZoUR<ADa0
 I<aR5RJ2c1Qba>GdC]KZCd2
 R1
 R2
- w1592238349
+ R17
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R17
+ Z33 !s108 1592320287.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@register
 vShiftLeft2
- !s110 1592304746
+ R32
 !i10b 1
 !s100 ]Zje9D[f?jFRnJBn`OeHc1
 I]0TYJ]_7?FkOoY=2GlT5=3
 R1
 R2
- w1591039219
+ R17
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R17
+ R33
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@shift@left2
 vSignExtend
 R0
@@ -521,18 +521,18 @@ R0
 IFBiMm>fY8WE23A[Ye;CUj3
 R1
 R2
- w1591039196
+ R17
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 L0 1
- R3
+ R4
 r1
 !s85 0
 31
- R4
+ R5
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
 !s101 -O0
 !i113 1
- R5
+ R6
 n@sign@extend
--- a/Project/MIPS/work/_lib.qdb
View file @19cd8e0
+++ b/Project/MIPS/work/_lib.qdb
View file @19cd8e0
--- a/Project/MIPS/work/_lib1_0.qdb deleted 100644 → 0
View file @30c9af9
+++ b/Project/MIPS/work/_lib1_0.qdb deleted 100644 → 0
View file @30c9af9
--- a/Project/MIPS/work/_lib1_3.qdb 0 → 100644
View file @19cd8e0
+++ b/Project/MIPS/work/_lib1_3.qdb 0 → 100644
View file @19cd8e0
--- a/Project/MIPS/work/_lib1_0.qpg → Project/MIPS/work/_lib1_3.qpg
View file @19cd8e0
+++ b/Project/MIPS/work/_lib1_0.qpg → Project/MIPS/work/_lib1_3.qpg
View file @19cd8e0
--- a/Project/MIPS/work/_lib1_0.qtl → Project/MIPS/work/_lib1_3.qtl
View file @19cd8e0
+++ b/Project/MIPS/work/_lib1_0.qtl → Project/MIPS/work/_lib1_3.qtl
View file @19cd8e0