2020-1-capstone-design1 / KNW_Project2

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...@@ -2,10 +2,11 @@ ...@@ -2,10 +2,11 @@
2 module HazardHandling(clk, 2 module HazardHandling(clk,
3 in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, // for data hazard handling 3 in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, // for data hazard handling
4 in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 4 in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
5 - in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, // for control hazard handling 5 + in_id_jump, in_id_branch, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, // for control hazard handling
6 out_stallsignal, out_flushsignal, out_nextPC); 6 out_stallsignal, out_flushsignal, out_nextPC);
7 input clk; 7 input clk;
8 input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch; 8 input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch;
9 +input[2:0] in_id_branch;
9 input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num; 10 input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
10 input[31:0] in_wb_nextPC; 11 input[31:0] in_wb_nextPC;
11 12
...@@ -13,15 +14,48 @@ output reg out_stallsignal; ...@@ -13,15 +14,48 @@ output reg out_stallsignal;
13 output reg[4:0] out_flushsignal; 14 output reg[4:0] out_flushsignal;
14 output reg[31:0] out_nextPC; 15 output reg[31:0] out_nextPC;
15 16
17 +reg isbranch;
16 reg[4:0] readreg2; 18 reg[4:0] readreg2;
17 19
18 initial begin 20 initial begin
21 + isbranch = 1'b0;
19 readreg2 <= 5'b00000; 22 readreg2 <= 5'b00000;
20 out_stallsignal <= 1'b0; 23 out_stallsignal <= 1'b0;
21 out_flushsignal <= 5'b00000; 24 out_flushsignal <= 5'b00000;
22 out_nextPC <= 32'h00000000; 25 out_nextPC <= 32'h00000000;
23 end 26 end
24 always @(negedge clk) begin 27 always @(negedge clk) begin
28 + if(isbranch == 1'b1 && in_ex_branch == 1'b1) begin
29 + out_flushsignal = 5'b11100;
30 + isbranch = 1'b0;
31 + end else begin
32 + isbranch = 1'b0;
33 +// Data Hazard Handling
34 + readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
35 + if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
36 + out_stallsignal = 1'b1;
37 + out_flushsignal = 5'b00100;
38 + end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
39 + out_stallsignal = 1'b1;
40 + out_flushsignal = 5'b00100;
41 + end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
42 + out_stallsignal = 1'b1;
43 + out_flushsignal = 5'b00100;
44 + end else begin
45 + out_stallsignal = 1'b0;
46 +
47 +// Control Hazard Handling
48 + if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
49 + else if(in_id_branch != 3'b000) isbranch = 1'b1;
50 + else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
51 + out_nextPC = in_wb_nextPC;
52 + out_flushsignal[4] = 1'b0;
53 + end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
54 + end
55 + end
56 +end
57 +/*
58 +always @(negedge clk) begin
25 // Data Hazard Handling 59 // Data Hazard Handling
26 readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2; 60 readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
27 if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin 61 if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
...@@ -45,6 +79,7 @@ always @(negedge clk) begin ...@@ -45,6 +79,7 @@ always @(negedge clk) begin
45 end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000; 79 end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
46 end 80 end
47 end 81 end
82 +*/
48 endmodule 83 endmodule
49 84
50 85
......
...@@ -4,51 +4,55 @@ input[31:0] address; ...@@ -4,51 +4,55 @@ input[31:0] address;
4 output reg[31:0] instruction; 4 output reg[31:0] instruction;
5 5
6 reg[31:0] instr_mem[127:0]; 6 reg[31:0] instr_mem[127:0];
7 -/*
8 -initial begin
9 7
10 -end 8 +// Factorial #1
11 -*/
12 -/*
13 initial begin 9 initial begin
14 -instr_mem[0] = 32'd0; 10 +instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
15 -instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 11 +instr_mem[1] = 32'b00100000000010000000000000001010; // addi, $0, $t0($8), +10
16 -instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 12 +instr_mem[2] = 32'b00100001001010010000000000000001; // addi, $t1($9), $t1($9), +1
17 -instr_mem[3] = 32'b00100101101011010000000000000011; // addi, $13 $13 3 13 +instr_mem[3] = 32'b00000010000010010000000000011000; // mult, $s0($16), $t1($9)
18 -instr_mem[4] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 14 +instr_mem[4] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
19 -instr_mem[5] = 32'd0; 15 +instr_mem[5] = 32'b00010101000010011111111111111100; // bne, $t0($8), $t1($9), -4
20 -instr_mem[6] = 32'b00100101101011010000000000000011; // addi, $13 $13 3 16 +instr_mem[6] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0
21 -instr_mem[7] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
22 -instr_mem[8] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
23 -instr_mem[9] = 32'd0;
24 -instr_mem[10] = 32'b00100101101011010000000000000011; // addi, $13 $13 3
25 -instr_mem[11] = 32'b00100100000010010000000000000001; // addi, $0 $9 1
26 -instr_mem[12] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
27 -instr_mem[13] = 32'd0;
28 end 17 end
29 -*/
30 18
19 +/*
20 +// Factorial #2
31 initial begin 21 initial begin
32 -instr_mem[0] = 32'b00100111000110000000000111111111; // addi, $24 $24 511 22 +instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
33 -instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 23 +instr_mem[1] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
34 -instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 24 +instr_mem[2] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
35 -instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9 25 +instr_mem[3] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
36 -instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10 26 +instr_mem[4] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
37 -instr_mem[5] = 32'b00010001000010100000000000000101; // beq, $8 $10 +5 27 +instr_mem[5] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
38 -instr_mem[6] = 32'b00000001000010010000000000011000; // mult, $8 $9 28 +instr_mem[6] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
39 -instr_mem[7] = 32'b00000001000000000111100000100000; // add, $8 $0 $15 29 +instr_mem[7] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
40 -instr_mem[8] = 32'd0; 30 +instr_mem[8] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
41 -instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12 31 +instr_mem[9] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
42 -instr_mem[10] = 32'b00000000000000000110100000010010; // mflo, $13 32 +instr_mem[10] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
43 -instr_mem[11] = 32'b10101100000010010000000000111100; // sw, $0 $9 60 33 +instr_mem[11] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
44 -instr_mem[12] = 32'd0; 34 +instr_mem[12] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
45 -instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1 35 +instr_mem[13] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
46 -instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60 36 +instr_mem[14] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
47 -instr_mem[15] = 32'b00001100000000000000000000010001; // jal, 17 37 +instr_mem[15] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
48 -instr_mem[16] = 32'b00000001000010010000000000011000; // mult, $8 $9 38 +instr_mem[16] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
49 -instr_mem[17] = 32'b00000000000000000000000000001000; // jr, $0 39 +instr_mem[17] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
50 -instr_mem[18] = 32'b00000001000010010000000000011000; // mult, $8 $9 40 +instr_mem[18] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
41 +instr_mem[19] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
42 +instr_mem[20] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
43 +instr_mem[21] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
44 +instr_mem[22] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
45 +instr_mem[23] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
46 +instr_mem[24] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
47 +instr_mem[25] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
48 +instr_mem[26] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
49 +instr_mem[27] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
50 +instr_mem[28] = 32'b00100001000010000000000000000001; // addi, $t0($8), $t0($8), +1
51 +instr_mem[29] = 32'b00000010000010000000000000011000; // mult, $s0($16), $t0($8)
52 +instr_mem[30] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
53 +instr_mem[31] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0
51 end 54 end
55 +*/
52 56
53 always @ (*) begin 57 always @ (*) begin
54 instruction = instr_mem[address/4]; 58 instruction = instr_mem[address/4];
......
1 -D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 1 +D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module Adder 3 +-- Compiling module MIPS_Pipeline_Forwarding
4 4
5 Top level modules: 5 Top level modules:
6 - Adder 6 + MIPS_Pipeline_Forwarding
7 7
8 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v 8 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 --- Compiling module MIPS_Pipeline_Forwarding 10 +-- Compiling module Adder
11 11
12 Top level modules: 12 Top level modules:
13 - MIPS_Pipeline_Forwarding 13 + Adder
14 14
15 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 15 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
16 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 16 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -33,6 +33,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -33,6 +33,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
33 Top level modules: 33 Top level modules:
34 Register 34 Register
35 35
36 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
37 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
38 +-- Compiling module MIPS_Pipeline
39 +
40 +Top level modules:
41 + MIPS_Pipeline
42 +
36 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 43 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
37 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 44 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
38 -- Compiling module PCregister 45 -- Compiling module PCregister
...@@ -48,13 +55,6 @@ Top level modules: ...@@ -48,13 +55,6 @@ Top level modules:
48 EX_MEM 55 EX_MEM
49 MEM_WB 56 MEM_WB
50 57
51 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
52 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
53 --- Compiling module MIPS_Pipeline
54 -
55 -Top level modules:
56 - MIPS_Pipeline
57 -
58 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 58 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
59 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 59 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
60 -- Compiling module HazardHandling 60 -- Compiling module HazardHandling
...@@ -66,13 +66,6 @@ Top level modules: ...@@ -66,13 +66,6 @@ Top level modules:
66 HazardHandling_Forwarding 66 HazardHandling_Forwarding
67 Mux_Forwarding 67 Mux_Forwarding
68 68
69 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
70 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
71 --- Compiling module SignExtend
72 -
73 -Top level modules:
74 - SignExtend
75 -
76 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 69 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
77 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 70 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
78 -- Compiling module Control 71 -- Compiling module Control
...@@ -80,12 +73,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -80,12 +73,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
80 Top level modules: 73 Top level modules:
81 Control 74 Control
82 75
83 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 76 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
84 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 77 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
85 --- Compiling module ALU 78 +-- Compiling module SignExtend
86 79
87 Top level modules: 80 Top level modules:
88 - ALU 81 + SignExtend
89 82
90 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 83 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
91 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 84 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -98,12 +91,12 @@ Top level modules: ...@@ -98,12 +91,12 @@ Top level modules:
98 Mux32bit 91 Mux32bit
99 MuxBranchSignal 92 MuxBranchSignal
100 93
101 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 94 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
102 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 95 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
103 --- Compiling module ShiftLeft2 96 +-- Compiling module ALU
104 97
105 Top level modules: 98 Top level modules:
106 - ShiftLeft2 99 + ALU
107 100
108 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} 101 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
109 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 102 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -112,7 +105,14 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -112,7 +105,14 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
112 Top level modules: 105 Top level modules:
113 DataMemory 106 DataMemory
114 107
115 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v 108 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
109 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
110 +-- Compiling module ShiftLeft2
111 +
112 +Top level modules:
113 + ShiftLeft2
114 +
115 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
116 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 116 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
117 -- Compiling module Clock 117 -- Compiling module Clock
118 -- Compiling module Clock_pipeline 118 -- Compiling module Clock_pipeline
......
...@@ -816,7 +816,7 @@ Resolution = ns ...@@ -816,7 +816,7 @@ Resolution = ns
816 UserTimeUnit = default 816 UserTimeUnit = default
817 817
818 ; Default run length 818 ; Default run length
819 -RunLength = 100 819 +RunLength = 100 ns
820 820
821 ; Maximum iterations that can be run without advancing simulation time 821 ; Maximum iterations that can be run without advancing simulation time
822 IterationLimit = 10000000 822 IterationLimit = 10000000
...@@ -2036,35 +2036,35 @@ Project_DefaultLib = work ...@@ -2036,35 +2036,35 @@ Project_DefaultLib = work
2036 Project_SortMethod = unused 2036 Project_SortMethod = unused
2037 Project_Files_Count = 15 2037 Project_Files_Count = 15
2038 Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 2038 Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
2039 -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039528 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 2039 +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
2040 Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v 2040 Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
2041 -Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592303982 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 2041 +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1592320265 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
2042 Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 2042 Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
2043 -Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592102255 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 2043 +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
2044 Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 2044 Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
2045 -Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592295803 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 2045 +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1592357286 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
2046 Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 2046 Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
2047 -Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238349 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 2047 +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
2048 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 2048 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
2049 -Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592266109 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 2049 +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
2050 Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 2050 Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
2051 -Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592293934 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 2051 +Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1592319215 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
2052 Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 2052 Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
2053 -Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592303944 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 2053 +Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1592320280 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
2054 Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 2054 Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
2055 -Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039196 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 2055 +Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
2056 Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 2056 Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
2057 -Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592280009 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 2057 +Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
2058 Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 2058 Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
2059 -Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238365 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 2059 +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
2060 Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 2060 Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
2061 -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452448 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 2061 +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
2062 Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 2062 Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
2063 -Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039219 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 2063 +Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318419 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
2064 Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v 2064 Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
2065 -Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238359 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 2065 +Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1592318418 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
2066 Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v 2066 Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
2067 -Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592091089 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 2067 +Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1592320589 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
2068 Project_Sim_Count = 0 2068 Project_Sim_Count = 0
2069 Project_Folder_Count = 0 2069 Project_Folder_Count = 0
2070 Echo_Compile_Output = 0 2070 Echo_Compile_Output = 0
......
...@@ -55,7 +55,7 @@ PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC); ...@@ -55,7 +55,7 @@ PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
55 HazardHandling hazardhandling(clk, 55 HazardHandling hazardhandling(clk,
56 ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, // for data hazard handling 56 ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, // for data hazard handling
57 ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, 57 ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,
58 - ctrl_jump, branch_signal, memwb_jump, memwb_branch, nextPC, 58 + ctrl_jump, ctrl_branch, branch_signal, memwb_jump, memwb_branch, nextPC,
59 stallsignal, flushsignal, flush_nextPC); 59 stallsignal, flushsignal, flush_nextPC);
60 60
61 // Instruction Fetch 61 // Instruction Fetch
......
...@@ -12,6 +12,6 @@ module Clock_pipeline(clk); ...@@ -12,6 +12,6 @@ module Clock_pipeline(clk);
12 output reg clk; 12 output reg clk;
13 13
14 initial clk = 0; 14 initial clk = 0;
15 -always #11 clk = ~clk; 15 +always #10 clk = ~clk;
16 endmodule 16 endmodule
17 17
......
No preview for this file type
...@@ -9,510 +9,510 @@ z2 ...@@ -9,510 +9,510 @@ z2
9 cModel Technology 9 cModel Technology
10 dC:/Modeltech_pe_edu_10.4a/examples 10 dC:/Modeltech_pe_edu_10.4a/examples
11 vAdder 11 vAdder
12 -Z0 !s110 1592304743 12 +Z0 !s110 1592320284
13 !i10b 1 13 !i10b 1
14 !s100 LKl?GBS:oo[A[hLP0Qb^_1 14 !s100 LKl?GBS:oo[A[hLP0Qb^_1
15 IlbJEP?2C3Ya>zhzD12^S]1 15 IlbJEP?2C3Ya>zhzD12^S]1
16 Z1 VDg1SIo80bB@j0V0VzS_@n1 16 Z1 VDg1SIo80bB@j0V0VzS_@n1
17 Z2 dD:/class/Capstone1/KNW_Project2/Project/MIPS 17 Z2 dD:/class/Capstone1/KNW_Project2/Project/MIPS
18 -w1591039528 18 +Z3 w1592318418
19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 19 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 20 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
21 L0 1 21 L0 1
22 -Z3 OP;L;10.4a;61 22 +Z4 OP;L;10.4a;61
23 r1 23 r1
24 !s85 0 24 !s85 0
25 31 25 31
26 -Z4 !s108 1592304743.000000 26 +Z5 !s108 1592320284.000000
27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
29 !s101 -O0 29 !s101 -O0
30 !i113 1 30 !i113 1
31 -Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0 31 +Z6 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
32 n@adder 32 n@adder
33 vALU 33 vALU
34 -Z6 !s110 1592304744 34 +R0
35 !i10b 1 35 !i10b 1
36 !s100 z[hZ0^@Q34FnkzY3g0ioc2 36 !s100 z[hZ0^@Q34FnkzY3g0ioc2
37 ImZ3]6XT73YVLGl?0_=9k33 37 ImZ3]6XT73YVLGl?0_=9k33
38 R1 38 R1
39 R2 39 R2
40 -w1592238365 40 +R3
41 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 41 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
42 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 42 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
43 L0 1 43 L0 1
44 -R3 44 +R4
45 r1 45 r1
46 !s85 0 46 !s85 0
47 31 47 31
48 -R4 48 +R5
49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
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452 -R13 452 +R16
453 !i10b 1 453 !i10b 1
454 !s100 ZWKU[XiaKQUFo0lg:i>8J3 454 !s100 ZWKU[XiaKQUFo0lg:i>8J3
455 IJN5hl<_id]kA5B6k4:9oE1 455 IJN5hl<_id]kA5B6k4:9oE1
456 R1 456 R1
457 R2 457 R2
458 -R14 458 +R17
459 -R15 459 +R18
460 -R16 460 +R19
461 L0 1 461 L0 1
462 -R3 462 +R4
463 r1 463 r1
464 !s85 0 464 !s85 0
465 31 465 31
466 -R17 466 +R20
467 -R18 467 +R21
468 -R19 468 +R22
469 !s101 -O0 469 !s101 -O0
470 !i113 1 470 !i113 1
471 -R5 471 +R6
472 n@p@cregister 472 n@p@cregister
473 vRegister 473 vRegister
474 -R13 474 +Z32 !s110 1592320287
475 !i10b 1 475 !i10b 1
476 !s100 bC`<7GaPg=bDaZoUR<ADa0 476 !s100 bC`<7GaPg=bDaZoUR<ADa0
477 I<aR5RJ2c1Qba>GdC]KZCd2 477 I<aR5RJ2c1Qba>GdC]KZCd2
478 R1 478 R1
479 R2 479 R2
480 -w1592238349 480 +R17
481 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 481 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
482 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 482 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
483 L0 1 483 L0 1
484 -R3 484 +R4
485 r1 485 r1
486 !s85 0 486 !s85 0
487 31 487 31
488 -R17 488 +Z33 !s108 1592320287.000000
489 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 489 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
490 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 490 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
491 !s101 -O0 491 !s101 -O0
492 !i113 1 492 !i113 1
493 -R5 493 +R6
494 n@register 494 n@register
495 vShiftLeft2 495 vShiftLeft2
496 -!s110 1592304746 496 +R32
497 !i10b 1 497 !i10b 1
498 !s100 ]Zje9D[f?jFRnJBn`OeHc1 498 !s100 ]Zje9D[f?jFRnJBn`OeHc1
499 I]0TYJ]_7?FkOoY=2GlT5=3 499 I]0TYJ]_7?FkOoY=2GlT5=3
500 R1 500 R1
501 R2 501 R2
502 -w1591039219 502 +R17
503 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 503 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
504 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 504 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
505 L0 1 505 L0 1
506 -R3 506 +R4
507 r1 507 r1
508 !s85 0 508 !s85 0
509 31 509 31
510 -R17 510 +R33
511 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 511 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
512 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 512 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
513 !s101 -O0 513 !s101 -O0
514 !i113 1 514 !i113 1
515 -R5 515 +R6
516 n@shift@left2 516 n@shift@left2
517 vSignExtend 517 vSignExtend
518 R0 518 R0
...@@ -521,18 +521,18 @@ R0 ...@@ -521,18 +521,18 @@ R0
521 IFBiMm>fY8WE23A[Ye;CUj3 521 IFBiMm>fY8WE23A[Ye;CUj3
522 R1 522 R1
523 R2 523 R2
524 -w1591039196 524 +R17
525 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 525 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
526 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 526 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
527 L0 1 527 L0 1
528 -R3 528 +R4
529 r1 529 r1
530 !s85 0 530 !s85 0
531 31 531 31
532 -R4 532 +R5
533 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v| 533 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
534 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v| 534 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
535 !s101 -O0 535 !s101 -O0
536 !i113 1 536 !i113 1
537 -R5 537 +R6
538 n@sign@extend 538 n@sign@extend
......
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