Mux.v
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module Mux5bit(input1, input2, signal, output1);
input[4:0] input1, input2;
input signal;
output reg[4:0] output1;
always @(*) begin
case(signal)
1'b0: output1 = input1;
1'b1: output1 = input2;
endcase
end
endmodule
module Mux32bit(input1, input2, signal, output1);
input[31:0] input1, input2;
input signal;
output reg[31:0] output1;
always @(*) begin
case(signal)
1'b0: output1 = input1;
1'b1: output1 = input2;
endcase
end
endmodule
module MuxBranchSignal(input1, signal, output1);
input[5:0] input1;
input[2:0] signal;
output reg output1;
always @(*) begin
case(signal)
3'b000: output1 = 1'b0;
3'b001: output1 = input1[0];
3'b010: output1 = input1[1];
3'b011: output1 = input1[2];
3'b100: output1 = input1[3];
3'b101: output1 = input1[4];
3'b110: output1 = input1[5];
endcase
end
endmodule