HazardHandling.v
8.18 KB
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// Hazard Handling ( No Fowarding )
module HazardHandling(clk,
in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, // for data hazard handling
in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
in_id_jump, in_id_branch, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, // for control hazard handling
out_stallsignal, out_flushsignal, out_nextPC);
input clk;
input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch;
input[2:0] in_id_branch;
input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
input[31:0] in_wb_nextPC;
output reg out_stallsignal;
output reg[4:0] out_flushsignal;
output reg[31:0] out_nextPC;
reg isbranch;
reg[4:0] readreg2;
initial begin
isbranch = 1'b0;
readreg2 <= 5'b00000;
out_stallsignal <= 1'b0;
out_flushsignal <= 5'b00000;
out_nextPC <= 32'h00000000;
end
always @(negedge clk) begin
if(isbranch == 1'b1 && in_ex_branch == 1'b1) begin
out_flushsignal = 5'b11100;
isbranch = 1'b0;
end else begin
isbranch = 1'b0;
// Data Hazard Handling
readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else begin
out_stallsignal = 1'b0;
// Control Hazard Handling
if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
else if(in_id_branch != 3'b000) isbranch = 1'b1;
else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
out_nextPC = in_wb_nextPC;
out_flushsignal[4] = 1'b0;
end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
end
end
end
/*
always @(negedge clk) begin
// Data Hazard Handling
readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else begin
out_stallsignal = 1'b0;
// Control Hazard Handling
if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
else if(in_ex_branch == 1'b1) out_flushsignal = 5'b11100;
else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
out_nextPC = in_wb_nextPC;
out_flushsignal[4] = 1'b0;
end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
end
end
*/
endmodule
// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
// Hazard Handling ( Fowarding )
// not finished
module HazardHandling_Forwarding(clk,
in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_ex_memtoreg, // for data hazard handling
in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
in_id_jump, in_id_jumpreg, in_ex_jumpreg, in_ex_branch, // for control hazard handling
in_id_PCjump, in_ex_PCjumpreg, in_ex_PCbranch,
out_stallsignal, out_flushsignal, out_fowardsig1, out_fowardsig2, out_nextPC);
input clk;
input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_ex_memtoreg, in_id_jump, in_id_jumpreg, in_ex_jumpreg, in_ex_branch;
input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
input[31:0] in_id_PCjump, in_ex_PCjumpreg, in_ex_PCbranch;
output reg out_stallsignal;
output reg[1:0] out_fowardsig1, out_fowardsig2;
output reg[4:0] out_flushsignal;
output reg[31:0] out_nextPC;
reg branchfinished;
reg[4:0] readreg2;
initial begin
branchfinished = 1'b0;
readreg2 = 5'b00000;
out_stallsignal = 1'b0;
out_flushsignal = 5'b00000;
out_fowardsig1 = 2'b00;
out_fowardsig2 = 2'b00;
out_nextPC = 32'h00000000;
end
always @(negedge clk) begin
// Data Hazard Handling
readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2) && in_ex_memtoreg==1'b1) begin
out_stallsignal = 1'b1;
out_flushsignal = 5'b00100;
end else begin
if(in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000 && in_ex_writereg_num==in_id_readreg_num1 && in_ex_memtoreg==1'b0) out_fowardsig1 = 2'b01;
else if(in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000 && in_mem_writereg_num==in_id_readreg_num1) out_fowardsig1 = 2'b10;
else if(in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000 && in_wb_writereg_num==in_id_readreg_num1) out_fowardsig1 = 2'b11;
else out_fowardsig1 = 2'b00;
if(in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000 && in_ex_writereg_num==readreg2 && in_ex_memtoreg==1'b0) out_fowardsig2 = 2'b01;
else if(in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000 && in_mem_writereg_num==readreg2) out_fowardsig2 = 2'b10;
else if(in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000 && in_wb_writereg_num==readreg2) out_fowardsig2 = 2'b11;
else out_fowardsig2 = 2'b00;
// Control Hazard Handling
if(branchfinished == 1'b1) begin
out_flushsignal[4] = 1'b0;
branchfinished = 1'b0;
end else if(in_id_jump == 1'b1 && in_id_jumpreg == 1'b0) begin
out_nextPC = in_id_PCjump;
out_flushsignal = 5'b11000;
branchfinished = 1'b1;
end else if(in_ex_jumpreg == 1'b1) begin
out_nextPC = in_ex_PCjumpreg;
out_flushsignal = 5'b11100;
branchfinished = 1'b1;
end else if(in_ex_branch == 1'b1) begin
out_nextPC = in_ex_PCbranch;
out_flushsignal = 5'b11100;
branchfinished = 1'b1;
end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
end
end
endmodule
module Mux_Forwarding(input1, input2, input3, input4, signal, output1);
input[31:0] input1, input2, input3, input4;
input[1:0] signal;
output reg[31:0] output1;
always @(*) begin
case(signal)
2'b00: output1 <= input1;
2'b01: output1 <= input2;
2'b10: output1 <= input3;
2'b11: output1 <= input4;
endcase
end
endmodule
// Control Hazard Handling
/*
module Flush_fowarding(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch,
out_flush, out_pc);
input clk;
input ctrl_jump, ctrl_jumpreg, ex_branchsignal;
input[2:0] ctrl_branch;
input[31:0] pc_jump, pc_jumpreg, ex_pc_branch;
output reg[4:0] out_flush;
output reg[31:0] out_pc;
reg isbranch;
initial begin
isbranch = 1'b0;
out_flush = 5'b00000;
out_pc = 32'h00000000;
end
always @(negedge clk) begin
if(isbranch == 1'b1) begin
if(ex_branchsignal == 1'b1) begin
out_pc = ex_pc_branch;
out_flush = 5'b11100;
end
isbranch = 1'b0;
end else begin
if(ctrl_jump == 1'b1) begin
out_flush = 5'b11000;
out_pc = (ctrl_jumpreg == 1'b0) ? pc_jump : pc_jumpreg;
end else if(ctrl_branch != 3'b000) isbranch = 1'b1;
else out_flush = 5'b00000;
end
end
endmodule
*/