module Register(clk, readin1, readin2, writein, writedata, regwrite, regout1, regout2);
input clk;
input[4:0] readin1, readin2, writein;
input[31:0] writedata;
input regwrite;
output[31:0] regout1, regout2;

integer i;
reg[31:0] register[31:0];

assign regout1 = register[readin1];
assign regout2 = register[readin2];

initial begin
	for(i=0; i<32; i=i+1) register[i] = 32'd0;
end

always @(negedge clk) begin
	if(regwrite == 1'b1 && writein != 5'd0) begin
		register[writein] = writedata;
	end
end

endmodule