module MIPS_SingleCycle;

wire clk;								// clock
reg[31:0] PC;								// program counter
reg[31:0] instr_address;
wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		

wire[31:0] instr;							// loaded instruction.

wire[4:0] temp_writereg, reg_writereg1;					// register number for the write data.
wire[31:0] temp_writedata, reg_writedata;				// data that will be written in the register.
wire[31:0] reg_readdata1, reg_readdata2;				// data from the requested register.

wire[31:0] alu_input2;							// input data of ALU.
wire[31:0] alu_result;							// result data of ALU.
wire[5:0] alu_branch;							// indicator for branch operation.

wire[31:0] mem_readdata;						// data from the requested address.

wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
wire[3:0] ctrl_aluctrl;
wire[2:0] ctrl_branch;							// control signals.

wire[31:0] extend_output;

wire[31:0] shiftBranch_output;
wire[31:0] shiftJump_output;


Clock clock(clk);
InstructionMemory instrmem(instr_address, instr);
Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata,  ctrl_regwrite,  reg_readdata1, reg_readdata2);
ALU alu(clk, reg_readdata1, alu_input2,  ctrl_aluctrl,  alu_result, alu_branch);
DataMemory datamem(clk, alu_result, reg_readdata2,  ctrl_memread, ctrl_memwrite,  mem_readdata);
Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);

Mux5bit mux_regdst(instr[20:16], instr[15:11],  ctrl_regdst,  temp_writereg);
Mux5bit mux_link_reg(temp_writereg, 5'b11111,  ctrl_link,  reg_writereg1);
MuxBranchSignal mux_branchsignal(alu_branch,  ctrl_branch,  branch_signal);
Mux32bit mux_alusrc(reg_readdata2, extend_output,  ctrl_alusrc,  alu_input2);
Mux32bit mux_memtoreg(alu_result, mem_readdata,  ctrl_memtoreg,  temp_writedata);
Mux32bit mux_link_data(temp_writedata, addPC4,  ctrl_link,  reg_writedata);
Mux32bit mux_branch(addPC4, addPCbranch,  branch_signal ,  tempPC_branch);
Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1,  ctrl_jumpreg,  tempPC_jump);
Mux32bit mux_jump(tempPC_branch, tempPC_jump,  ctrl_jump,  nextPC);
SignExtend extend(instr[15:0], extend_output);
Adder add_pc4(PC, 32'h00000004, addPC4);
Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);

initial begin
	PC = 32'h00000000;
end

always @(posedge clk) begin
	case(nextPC[31])					// if nextPC is available, PC = nextPC.
		1'b0: PC = nextPC;
		1'b1: PC = nextPC;
	endcase

	instr_address = PC;
end

endmodule