// Test Required
module MIPS_Pipeline;

wire clk;
wire stallsignal;
wire flush_jump, flush_branch;
wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC, flush_pc;

wire[31:0] instr;						// loaded instruction.

wire[4:0] temp_writereg, reg_writereg1;				// register number for the write data.
wire[31:0] temp_writedata, reg_writedata;			// data that will be written in the register.
wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.

wire[31:0] alu_input2;						// input data of ALU.
wire[31:0] alu_result;						// result data of ALU.
wire[5:0] alu_branch;						// indicator for branch operation.

wire[31:0] mem_readdata;					// data from the requested address.

wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
wire[3:0] ctrl_aluctrl;						// control signals.
wire[2:0] ctrl_branch;

wire[31:0] extend_output;

wire[31:0] shiftBranch_output;
wire[31:0] shiftJump_output;

// IF_ID register outputs
wire[31:0] ifid_instr, ifid_PC_4;

// ID_EX register outputs
wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg, idex_link;
wire[3:0] idex_aluctrl; 
wire[2:0] idex_branch;
wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;

// EX_MEM register outputs
wire[4:0] exmem_writereg1;
wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link;
wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;

// MEM_WB register outputs
wire[4:0] memwb_writereg1;
wire memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link;
wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch;

wire temp;
assign temp = 1'b0;

Clock clock(clk);
PCcounter pccounter(clk, stallsignal, (flush_jump|flush_branch), flush_pc, instr_address);
Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, stallsignal);
Flush flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, branch_signal, {ifid_PC_4[31:28], shiftJump_output[27:0]}, reg_readdata1, addPCbranch, 
	flush_jump, flush_branch, flush_pc);

// Instruction Fetch
InstructionMemory instrmem(instr_address, instr);
Adder add_pc4(instr_address, 32'h00000004, addPC4);

IF_ID ifid(clk, stallsignal, 
	(flush_jump|flush_branch), instr, addPC4, 
	ifid_instr, ifid_PC_4);

// Instruction Decode
Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], 
	ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11],  ctrl_regdst,  temp_writereg);
Mux5bit mux_link_reg(temp_writereg, 5'b11111,  ctrl_link,  reg_writereg1);
Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata,  memwb_regwrite,  reg_readdata1, reg_readdata2);
SignExtend extend(ifid_instr[15:0], extend_output);
ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);

ID_EX idex(clk, stallsignal, flush_branch, 
	reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link, 
	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, 
	idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link, 
	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);

// Execute
Mux32bit mux_alusrc(idex_readdata2, idex_extenddata,  idex_alusrc,  alu_input2);
ALU alu(clk, idex_readdata1, alu_input2,  idex_aluctrl,  alu_result, alu_branch);
ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);

EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link, 
	alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 
	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 
	exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);

// Memory
DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exmem_memwrite,  mem_readdata);
Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch,  exmem_branch ,  tempPC_branch);

MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, exmem_link, 
	exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, tempPC_branch, 
	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link, 
	memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch);

// Writeback
Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  temp_writedata);
Mux32bit mux_link_data(temp_writedata, memwb_PC_4,  memwb_link,  reg_writedata);
Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump,  memwb_jump,  nextPC);


always @(posedge clk) begin
end

endmodule