asimd-st2.s
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
st2 {v0.s, v1.s}[0], [sp]
st2 {v0.2s, v1.2s}, [sp]
st2 {v0.d, v1.d}[0], [sp]
st2 {v0.2d, v1.2d}, [sp]
st2 {v0.s, v1.s}[0], [sp], #8
st2 {v0.2s, v1.2s}, [sp], #16
st2 {v0.d, v1.d}[0], [sp], #16
st2 {v0.2d, v1.2d}, [sp], #32
st2 {v0.s, v1.s}[0], [sp], x0
st2 {v0.2s, v1.2s}, [sp], x0
st2 {v0.d, v1.d}[0], [sp], x0
st2 {v0.2d, v1.2d}, [sp], x0
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 1200
# M3-NEXT: Total Cycles: 8703
# M3-NEXT: Total uOps: 5400
# M4-NEXT: Total Cycles: 2403
# M4-NEXT: Total uOps: 2300
# M5-NEXT: Total Cycles: 2403
# M5-NEXT: Total uOps: 2000
# ALL: Dispatch Width: 6
# M3-NEXT: uOps Per Cycle: 0.62
# M3-NEXT: IPC: 0.14
# M3-NEXT: Block RThroughput: 40.5
# M4-NEXT: uOps Per Cycle: 0.96
# M4-NEXT: IPC: 0.50
# M4-NEXT: Block RThroughput: 7.5
# M5-NEXT: uOps Per Cycle: 0.83
# M5-NEXT: IPC: 0.50
# M5-NEXT: Block RThroughput: 7.5
# ALL: Instruction Info:
# ALL-NEXT: [1]: #uOps
# ALL-NEXT: [2]: Latency
# ALL-NEXT: [3]: RThroughput
# ALL-NEXT: [4]: MayLoad
# ALL-NEXT: [5]: MayStore
# ALL-NEXT: [6]: HasSideEffects (U)
# ALL: [1] [2] [3] [4] [5] [6] Instructions:
# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp]
# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp]
# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp]
# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp]
# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp], #8
# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp], #16
# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp], #16
# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp], #32
# M3-NEXT: 4 7 3.00 * st2 { v0.s, v1.s }[0], [sp], x0
# M3-NEXT: 4 7 3.00 * st2 { v0.2s, v1.2s }, [sp], x0
# M3-NEXT: 4 7 3.00 * st2 { v0.d, v1.d }[0], [sp], x0
# M3-NEXT: 6 8 4.50 * st2 { v0.2d, v1.2d }, [sp], x0
# M4-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp]
# M4-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp]
# M4-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp]
# M4-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp]
# M4-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], #8
# M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], #16
# M4-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], #16
# M4-NEXT: 3 2 1.00 * st2 { v0.2d, v1.2d }, [sp], #32
# M4-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], x0
# M4-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x0
# M4-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], x0
# M4-NEXT: 3 2 1.00 * st2 { v0.2d, v1.2d }, [sp], x0
# M5-NEXT: 1 2 0.50 * st2 { v0.s, v1.s }[0], [sp]
# M5-NEXT: 1 2 0.50 * st2 { v0.2s, v1.2s }, [sp]
# M5-NEXT: 1 2 0.50 * st2 { v0.d, v1.d }[0], [sp]
# M5-NEXT: 1 2 1.00 * st2 { v0.2d, v1.2d }, [sp]
# M5-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], #8
# M5-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], #16
# M5-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], #16
# M5-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp], #32
# M5-NEXT: 2 2 0.50 * st2 { v0.s, v1.s }[0], [sp], x0
# M5-NEXT: 2 2 0.50 * st2 { v0.2s, v1.2s }, [sp], x0
# M5-NEXT: 2 2 0.50 * st2 { v0.d, v1.d }[0], [sp], x0
# M5-NEXT: 2 2 1.00 * st2 { v0.2d, v1.2d }, [sp], x0