WebAssembly.td
4.65 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This is a target description file for the WebAssembly architecture,
/// which is also known as "wasm".
///
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// WebAssembly Subtarget features.
//===----------------------------------------------------------------------===//
def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
"Enable 128-bit SIMD">;
def FeatureUnimplementedSIMD128 :
SubtargetFeature<"unimplemented-simd128",
"SIMDLevel", "UnimplementedSIMD128",
"Enable 128-bit SIMD not yet implemented in engines",
[FeatureSIMD128]>;
def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
"Enable Atomics">;
def FeatureNontrappingFPToInt :
SubtargetFeature<"nontrapping-fptoint",
"HasNontrappingFPToInt", "true",
"Enable non-trapping float-to-int conversion operators">;
def FeatureSignExt :
SubtargetFeature<"sign-ext",
"HasSignExt", "true",
"Enable sign extension operators">;
def FeatureTailCall :
SubtargetFeature<"tail-call",
"HasTailCall", "true",
"Enable tail call instructions">;
def FeatureExceptionHandling :
SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
"Enable Wasm exception handling">;
def FeatureBulkMemory :
SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
"Enable bulk memory operations">;
def FeatureMultivalue :
SubtargetFeature<"multivalue",
"HasMultivalue", "true",
"Enable multivalue blocks, instructions, and functions">;
def FeatureMutableGlobals :
SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true",
"Enable mutable globals">;
//===----------------------------------------------------------------------===//
// Architectures.
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "WebAssemblyRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "WebAssemblyInstrInfo.td"
def WebAssemblyInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// WebAssembly Processors supported.
//===----------------------------------------------------------------------===//
// Minimal Viable Product.
def : ProcessorModel<"mvp", NoSchedModel, []>;
// Generic processor: latest stable version.
def : ProcessorModel<"generic", NoSchedModel, []>;
// Latest and greatest experimental version of WebAssembly. Bugs included!
def : ProcessorModel<"bleeding-edge", NoSchedModel,
[FeatureSIMD128, FeatureAtomics,
FeatureNontrappingFPToInt, FeatureSignExt,
FeatureMutableGlobals]>;
//===----------------------------------------------------------------------===//
// Target Declaration
//===----------------------------------------------------------------------===//
def WebAssemblyAsmParser : AsmParser {
// The physical register names are not in the binary format or asm text
let ShouldEmitMatchRegisterName = 0;
}
def WebAssemblyAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
int PassSubtarget = 0;
int Variant = 0;
bit isMCAsmWriter = 1;
}
def WebAssembly : Target {
let InstructionSet = WebAssemblyInstrInfo;
let AssemblyParsers = [WebAssemblyAsmParser];
let AssemblyWriters = [WebAssemblyAsmWriter];
}