smem-war-hazard.mir
9.3 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: hazard_smem_war
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_no_hazard
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_no_hazard
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr3 = S_ADD_U32 $sgpr4, $sgpr5, implicit-def $scc
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_dependent_salu
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_dependent_salu
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 0
$sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_independent_salu
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_ADD_U32
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_independent_salu
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 0
$sgpr3 = S_ADD_U32 $sgpr5, $sgpr4, implicit-def $scc
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_smem
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_LOAD_DWORD_IMM
# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_smem
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr6, $sgpr7, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr5 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0, 0
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_waitcnt_0
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_waitcnt_0
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 0
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_vmcnt_0
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT 3952{{$}}
# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_vmcnt_0
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 3952
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_expcnt_0
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT 53007{{$}}
# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_expcnt_0
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 53007
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_lgkmcnt_0
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT 49279{{$}}
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_lgkmcnt_0
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT 49279
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_0
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT_LGKMCNT
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_waitcnt_lgkmcnt_0
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT_LGKMCNT $sgpr_null, 0
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_1
# GCN: S_LOAD_DWORD_IMM
# GCN-NEXT: S_WAITCNT_LGKMCNT
# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_only_waitcnt_lgkmcnt_1
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_WAITCNT_LGKMCNT $sgpr_null, 1
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_branch
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_branch
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
successors: %bb.1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_BRANCH %bb.1
bb.1:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_cbranch
# GCN: S_AND_B64
# GCN: S_LOAD_DWORD_IMM
# GCN: S_CBRANCH_VCCZ
# GCN-NOT: $sgpr_null = S_MOV_B32 0
# GCN: V_CMP_EQ_F32
# GCN: S_ENDPGM 0
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_cbranch
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
successors: %bb.1, %bb.2
$vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
bb.1:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
bb.2:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_cbranch_carry
# GCN: S_AND_B64
# GCN: S_LOAD_DWORD_IMM
# GCN: S_CBRANCH_VCCZ
# GCN-NOT: $sgpr_null = S_MOV_B32 0
# GCN: V_CMP_EQ_F32
# GCN-NEXT: S_ENDPGM 0
# GCN-NOT: $sgpr_null = S_MOV_B32 0
# GCN: V_CMP_EQ_F32
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_cbranch_carry
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
successors: %bb.1, %bb.2
$vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
bb.1:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
bb.2:
successors: %bb.3
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
bb.3:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_backedge
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
# GCN: S_LOAD_DWORD_IMM
---
name: hazard_smem_war_backedge
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
successors: %bb.1
$sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
bb.1:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
S_BRANCH %bb.0
...
# GCN-LABEL: name: hazard_smem_war_impdef
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_CMP_EQ_F32
---
name: hazard_smem_war_impdef
body: |
bb.0:
liveins: $vcc, $vgpr0
$sgpr0 = S_LOAD_DWORD_IMM $vcc, 0, 0, 0
V_CMP_EQ_F32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $exec
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_readlane
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_READLANE_B32
---
name: hazard_smem_war_readlane
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr0 = V_READLANE_B32 $vgpr0, $sgpr3
S_ENDPGM 0
...
# Workaround since spilling/restoring SGPRs use real opcodes.
# GCN-LABEL: name: hazard_smem_war_readlane_gfx10
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_READLANE_B32_gfx10
---
name: hazard_smem_war_readlane_gfx10
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_readfirstlane
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_READFIRSTLANE_B32
---
name: hazard_smem_war_readfirstlane
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
S_ENDPGM 0
...