andorn2.ll
2.94 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
; GCN-LABEL: {{^}}scalar_andn2_i32_one_use
; GCN: s_andn2_b32
define amdgpu_kernel void @scalar_andn2_i32_one_use(
i32 addrspace(1)* %r0, i32 %a, i32 %b) {
entry:
%nb = xor i32 %b, -1
%r0.val = and i32 %a, %nb
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}scalar_andn2_i64_one_use
; GCN: s_andn2_b64
define amdgpu_kernel void @scalar_andn2_i64_one_use(
i64 addrspace(1)* %r0, i64 %a, i64 %b) {
entry:
%nb = xor i64 %b, -1
%r0.val = and i64 %a, %nb
store i64 %r0.val, i64 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}scalar_orn2_i32_one_use
; GCN: s_orn2_b32
define amdgpu_kernel void @scalar_orn2_i32_one_use(
i32 addrspace(1)* %r0, i32 %a, i32 %b) {
entry:
%nb = xor i32 %b, -1
%r0.val = or i32 %a, %nb
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}scalar_orn2_i64_one_use
; GCN: s_orn2_b64
define amdgpu_kernel void @scalar_orn2_i64_one_use(
i64 addrspace(1)* %r0, i64 %a, i64 %b) {
entry:
%nb = xor i64 %b, -1
%r0.val = or i64 %a, %nb
store i64 %r0.val, i64 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}vector_andn2_i32_s_v_one_use
; GCN: v_not_b32
; GCN: v_and_b32
define amdgpu_kernel void @vector_andn2_i32_s_v_one_use(
i32 addrspace(1)* %r0, i32 %s) {
entry:
%v = call i32 @llvm.amdgcn.workitem.id.x() #1
%not = xor i32 %v, -1
%r0.val = and i32 %s, %not
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}vector_andn2_i32_v_s_one_use
; GCN: s_not_b32
; GCN: v_and_b32
define amdgpu_kernel void @vector_andn2_i32_v_s_one_use(
i32 addrspace(1)* %r0, i32 %s) {
entry:
%v = call i32 @llvm.amdgcn.workitem.id.x() #1
%not = xor i32 %s, -1
%r0.val = and i32 %v, %not
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}vector_orn2_i32_s_v_one_use
; GCN: v_not_b32
; GCN: v_or_b32
define amdgpu_kernel void @vector_orn2_i32_s_v_one_use(
i32 addrspace(1)* %r0, i32 %s) {
entry:
%v = call i32 @llvm.amdgcn.workitem.id.x() #1
%not = xor i32 %v, -1
%r0.val = or i32 %s, %not
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}vector_orn2_i32_v_s_one_use
; GCN: s_not_b32
; GCN: v_or_b32
define amdgpu_kernel void @vector_orn2_i32_v_s_one_use(
i32 addrspace(1)* %r0, i32 %s) {
entry:
%v = call i32 @llvm.amdgcn.workitem.id.x() #1
%not = xor i32 %s, -1
%r0.val = or i32 %v, %not
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; Function Attrs: nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.x() #0