legalize-flog10.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_flog10_s32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_flog10_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[FLOG10_:%[0-9]+]]:_(s32) = G_FLOG10 [[COPY]]
; CHECK: $vgpr0 = COPY [[FLOG10_]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FLOG10 %0
$vgpr0 = COPY %1
...
---
name: test_flog10_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_flog10_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[FLOG10_:%[0-9]+]]:_(s32) = G_FLOG10 [[UV]]
; CHECK: [[FLOG10_1:%[0-9]+]]:_(s32) = G_FLOG10 [[UV1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FLOG10_]](s32), [[FLOG10_1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_FLOG10 %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_flog10_v3s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: test_flog10_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[FLOG10_:%[0-9]+]]:_(s32) = G_FLOG10 [[UV]]
; CHECK: [[FLOG10_1:%[0-9]+]]:_(s32) = G_FLOG10 [[UV1]]
; CHECK: [[FLOG10_2:%[0-9]+]]:_(s32) = G_FLOG10 [[UV2]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FLOG10_]](s32), [[FLOG10_1]](s32), [[FLOG10_2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = G_FLOG10 %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...