global-value.ll
9.15 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=HSA %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=PAL %s
@external_constant = external addrspace(4) constant i32, align 4
@external_constant32 = external addrspace(6) constant i32, align 4
@external_global = external addrspace(1) global i32, align 4
@internal_constant = internal addrspace(4) constant i32 9, align 4
@internal_constant32 = internal addrspace(6) constant i32 9, align 4
@internal_global = internal addrspace(1) global i32 9, align 4
define i32 addrspace(4)* @external_constant_got() {
; HSA-LABEL: name: external_constant_got
; HSA: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant + 4, target-flags(amdgpu-gotprel32-hi) @external_constant + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p4)
; HSA: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: external_constant_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @external_constant + 4, 0, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(4)* @external_constant
}
define i32 addrspace(1)* @external_global_got() {
; HSA-LABEL: name: external_global_got
; HSA: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; HSA: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: external_global_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 4, implicit-def $scc
; PAL: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(1)* @external_global
}
define i32 addrspace(4)* @internal_constant_pcrel() {
; HSA-LABEL: name: internal_constant_pcrel
; HSA: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdgpu-rel32-hi) @internal_constant + 4, implicit-def $scc
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; HSA: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: internal_constant_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @internal_constant + 4, 0, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(4)* @internal_constant
}
define i32 addrspace(1)* @internal_global_pcrel() {
; HSA-LABEL: name: internal_global_pcrel
; HSA: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 4, implicit-def $scc
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
; HSA: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: internal_global_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 4, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(1)* @internal_global
}
define i32 addrspace(6)* @external_constant32_got() {
; HSA-LABEL: name: external_constant32_got
; HSA: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32 + 4, target-flags(amdgpu-gotprel32-hi) @external_constant32 + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0
; HSA: $vgpr0 = COPY [[EXTRACT]](p6)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
; PAL-LABEL: name: external_constant32_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @external_constant32 + 4, 0, implicit-def $scc
; PAL: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; PAL: $vgpr0 = COPY [[EXTRACT]](p6)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
ret i32 addrspace(6)* @external_constant32
}
define i32 addrspace(6)* @internal_constant32_pcrel() {
; HSA-LABEL: name: internal_constant32_pcrel
; HSA: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amdgpu-rel32-hi) @internal_constant32 + 4, implicit-def $scc
; HSA: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; HSA: $vgpr0 = COPY [[EXTRACT]](p6)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
; PAL-LABEL: name: internal_constant32_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @internal_constant32 + 4, 0, implicit-def $scc
; PAL: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; PAL: $vgpr0 = COPY [[EXTRACT]](p6)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
ret i32 addrspace(6)* @internal_constant32
}