testComparesllneull.ll
7.3 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8
define i64 @test_llneull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_z(i64 %a) {
; CHECK-LABEL: test_llneull_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addic r4, r3, -1
; CHECK-BE-NEXT: subfe r3, r4, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_sext_z(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llneull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: addic r4, r3, -1
; CHECK-LE-NEXT: subfe r3, r4, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r5, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addic r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r5, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llneull_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfic r3, r3, 0
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llneull_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: subfic r3, r3, 0
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}