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샘플 명령어 세트 추가, 발표 ppt 자료 추가 및 최종 보고서 제출

...@@ -5,6 +5,7 @@ output reg[31:0] instruction; ...@@ -5,6 +5,7 @@ output reg[31:0] instruction;
5 5
6 reg[31:0] instr_mem[127:0]; 6 reg[31:0] instr_mem[127:0];
7 7
8 +/*
8 // Factorial #1 9 // Factorial #1
9 initial begin 10 initial begin
10 instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1 11 instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
...@@ -15,6 +16,7 @@ instr_mem[4] = 32'b00000000000000001000000000010010; // mflo, $s0($16) ...@@ -15,6 +16,7 @@ instr_mem[4] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
15 instr_mem[5] = 32'b00010101000010011111111111111100; // bne, $t0($8), $t1($9), -4 16 instr_mem[5] = 32'b00010101000010011111111111111100; // bne, $t0($8), $t1($9), -4
16 instr_mem[6] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0 17 instr_mem[6] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0
17 end 18 end
19 +*/
18 20
19 /* 21 /*
20 // Factorial #2 22 // Factorial #2
...@@ -54,6 +56,40 @@ instr_mem[31] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2 ...@@ -54,6 +56,40 @@ instr_mem[31] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2
54 end 56 end
55 */ 57 */
56 58
59 +// No Hazard
60 +initial begin
61 +instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
62 +instr_mem[1] = 32'b00100000000010000000000000000001; // addi, $0, $t0($8), +1
63 +instr_mem[2] = 32'b00100000000010010000000000000010; // addi, $0, $t1($9), +2
64 +instr_mem[3] = 32'b00100000000010100000000000000011; // addi, $0, $t2($10), +3
65 +instr_mem[4] = 32'b00100000000010110000000000000100; // addi, $0, $t3($11), +4
66 +instr_mem[5] = 32'b00100000000011000000000000000101; // addi, $0, $t4($12), +5
67 +instr_mem[6] = 32'b00100000000011010000000000000110; // addi, $0, $t5($13), +6
68 +instr_mem[7] = 32'b00000001000010000000000000011000; // mult, $t0($08), $t0($8)
69 +instr_mem[8] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
70 +instr_mem[9] = 32'b00000001000010010000000000011000; // mult, $t0($08), $t1($9)
71 +instr_mem[10] = 32'b00000000000000001000100000010010; // mflo, $s1($17)
72 +instr_mem[11] = 32'b00000001001010010000000000011000; // mult, $t1($9), $t1($9)
73 +instr_mem[12] = 32'b00000000000000001001000000010010; // mflo, $s2($18)
74 +instr_mem[13] = 32'b00000000000000001001100000010010; // mflo, $s3($19)
75 +instr_mem[14] = 32'b00100000000000100000000000011000; // addi, $0, $v0($2), +24
76 +instr_mem[15] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
77 +instr_mem[16] = 32'b00100000000010000000000000000001; // addi, $0, $t0($8), +1
78 +instr_mem[17] = 32'b00100000000010010000000000000010; // addi, $0, $t1($9), +2
79 +instr_mem[18] = 32'b00100000000010100000000000000011; // addi, $0, $t2($10), +3
80 +instr_mem[19] = 32'b00100000000010110000000000000100; // addi, $0, $t3($11), +4
81 +instr_mem[20] = 32'b00100000000011000000000000000101; // addi, $0, $t4($12), +5
82 +instr_mem[21] = 32'b00100000000011010000000000000110; // addi, $0, $t5($13), +6
83 +instr_mem[22] = 32'b00000001000010000000000000011000; // mult, $t0($08), $t0($8)
84 +instr_mem[23] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
85 +instr_mem[24] = 32'b00000001000010010000000000011000; // mult, $t0($08), $t1($9)
86 +instr_mem[25] = 32'b00000000000000001000100000010010; // mflo, $s1($17)
87 +instr_mem[26] = 32'b00000001001010010000000000011000; // mult, $t1($9), $t1($9)
88 +instr_mem[27] = 32'b00000000000000001001000000010010; // mflo, $s2($18)
89 +instr_mem[28] = 32'b00000000000000001001100000010010; // mflo, $s3($19)
90 +instr_mem[29] = 32'b00100000000000100000000000111000; // addi, $0, $v0($2), +56
91 +end
92 +
57 always @ (*) begin 93 always @ (*) begin
58 instruction = instr_mem[address/4]; 94 instruction = instr_mem[address/4];
59 end 95 end
......
1 -D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v 1 +D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module MIPS_Pipeline_Forwarding 3 +-- Compiling module Adder
4 4
5 Top level modules: 5 Top level modules:
6 - MIPS_Pipeline_Forwarding 6 + Adder
7 7
8 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v 8 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 9 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 --- Compiling module Adder 10 +-- Compiling module MIPS_Pipeline_Forwarding
11 11
12 Top level modules: 12 Top level modules:
13 - Adder 13 + MIPS_Pipeline_Forwarding
14 14
15 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 15 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
16 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 16 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -33,13 +33,6 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -33,13 +33,6 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
33 Top level modules: 33 Top level modules:
34 Register 34 Register
35 35
36 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
37 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
38 --- Compiling module MIPS_Pipeline
39 -
40 -Top level modules:
41 - MIPS_Pipeline
42 -
43 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 36 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
44 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 37 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
45 -- Compiling module PCregister 38 -- Compiling module PCregister
...@@ -55,6 +48,13 @@ Top level modules: ...@@ -55,6 +48,13 @@ Top level modules:
55 EX_MEM 48 EX_MEM
56 MEM_WB 49 MEM_WB
57 50
51 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
52 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
53 +-- Compiling module MIPS_Pipeline
54 +
55 +Top level modules:
56 + MIPS_Pipeline
57 +
58 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 58 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
59 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 59 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
60 -- Compiling module HazardHandling 60 -- Compiling module HazardHandling
...@@ -66,6 +66,13 @@ Top level modules: ...@@ -66,6 +66,13 @@ Top level modules:
66 HazardHandling_Forwarding 66 HazardHandling_Forwarding
67 Mux_Forwarding 67 Mux_Forwarding
68 68
69 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
70 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
71 +-- Compiling module SignExtend
72 +
73 +Top level modules:
74 + SignExtend
75 +
69 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 76 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
70 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 77 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
71 -- Compiling module Control 78 -- Compiling module Control
...@@ -73,12 +80,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -73,12 +80,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
73 Top level modules: 80 Top level modules:
74 Control 81 Control
75 82
76 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 83 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
77 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 84 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
78 --- Compiling module SignExtend 85 +-- Compiling module ALU
79 86
80 Top level modules: 87 Top level modules:
81 - SignExtend 88 + ALU
82 89
83 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 90 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
84 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 91 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -91,12 +98,12 @@ Top level modules: ...@@ -91,12 +98,12 @@ Top level modules:
91 Mux32bit 98 Mux32bit
92 MuxBranchSignal 99 MuxBranchSignal
93 100
94 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v 101 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
95 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 102 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
96 --- Compiling module ALU 103 +-- Compiling module ShiftLeft2
97 104
98 Top level modules: 105 Top level modules:
99 - ALU 106 + ShiftLeft2
100 107
101 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} 108 } {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
102 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 109 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
...@@ -105,14 +112,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 ...@@ -105,14 +112,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
105 Top level modules: 112 Top level modules:
106 DataMemory 113 DataMemory
107 114
108 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 115 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
109 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
110 --- Compiling module ShiftLeft2
111 -
112 -Top level modules:
113 - ShiftLeft2
114 -
115 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
116 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 116 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
117 -- Compiling module Clock 117 -- Compiling module Clock
118 -- Compiling module Clock_pipeline 118 -- Compiling module Clock_pipeline
......
This diff is collapsed. Click to expand it.
1 -module test;
2 -wire clk;
3 -wire stall;
4 -wire[4:0] in1, out1, out2, out3, out4, out5, out6;
5 -wire stall_1;
6 -
7 -assign stall_1 = 0;
8 -
9 -Clock clock(clk);
10 -testPC tpc(clk, stall, in1);
11 -testA ta1(clk, stall, in1, out1);
12 -testA ta2(clk, stall, out1, out2);
13 -testA ta3(clk, stall, out2, out3);
14 -testA ta4(clk, stall_1, out3, out4);
15 -testA ta5(clk, stall_1, out4, out5);
16 -testA ta6(clk, stall_1, out5, out6);
17 -testB stl(clk, out1, stall);
18 -
19 -initial begin
20 -end
21 -endmodule
22 -
23 -
24 -module testA(clk, stall, in1, out1);
25 -input clk, stall;
26 -input[4:0] in1;
27 -output reg[4:0] out1;
28 -
29 -reg[4:0] temp1;
30 -reg stallfinished;
31 -
32 -initial begin
33 - temp1 = 5'b00000;
34 - out1 = 5'b00000;
35 - stallfinished = 1'b0;
36 -end
37 -
38 -always @(posedge clk) begin
39 - if(stall == 1'b1) out1 <= 5'b00000;
40 - else if(stallfinished == 1'b1) begin
41 - out1 <= temp1;
42 - stallfinished <= 1'b0;
43 - end
44 - else out1 <= in1;
45 -end
46 -always @(posedge stall) begin
47 - temp1 = in1;
48 -end
49 -always @(negedge stall) begin
50 - stallfinished = 1'b1;
51 -end
52 -endmodule
53 -
54 -
55 -module testB(clk, out1, stall);
56 -input clk;
57 -input[4:0] out1;
58 -output reg stall;
59 -
60 -integer i;
61 -
62 -initial begin
63 - stall = 1'b0;
64 - i = 0;
65 -end
66 -
67 -always @(negedge clk)
68 - if(i > 0) i = i-1;
69 - else begin
70 - if(out1 == 5'b00101) begin
71 - i = 2;
72 - stall = 1'b1;
73 - end
74 - else stall = 1'b0;
75 - end
76 -endmodule
77 -
78 -
79 -module testPC(clk, stall, in1);
80 -input clk, stall;
81 -output reg[4:0] in1;
82 -
83 -reg[4:0] PC;
84 -
85 -initial begin
86 - PC = 5'd0;
87 -end
88 -always @(posedge clk) begin
89 - if(stall == 1'b0) PC <= PC+1;
90 - in1 <= PC;
91 -end
92 -endmodule
93 -
94 -/*
95 -module test;
96 -
97 -wire clk;
98 -reg sig1;
99 -reg[31:0] in1;
100 -wire[31:0] out1, out2;
101 -
102 -Clock clock(clk);
103 -testA ta(clk, sig1, in1, out1, out2);
104 -
105 -initial begin
106 - sig1 <= 1'b0;
107 - in1 <= 32'd0;
108 - #100;
109 - in1 <= 32'hffffffff;
110 - #100;
111 - sig1 <= 1'b1;
112 - in1 <= 32'h0000ffff;
113 - #100;
114 - sig1 <= 1'b1;
115 - in1 <= 32'hffff0000;
116 - #100;
117 -end
118 -
119 -endmodule
120 -
121 -module testA(clk, sig1, in1, out1, out2);
122 -
123 -input clk, sig1;
124 -input[31:0] in1;
125 -output reg[31:0] out1, out2;
126 -
127 -always @(posedge clk) begin
128 - out1 <= in1;
129 - if(sig1 == 1) out2 <= in1;
130 -end
131 -
132 -endmodule
133 -*/
...\ No newline at end of file ...\ No newline at end of file
1 -module testbench;
2 -
3 -wire clk; // clock
4 -reg[31:0] PC; // program counter
5 -reg[31:0] instr_address;
6 -wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
7 -
8 -wire[31:0] instr; // loaded instruction.
9 -
10 -wire[4:0] reg_writereg1; // register number for the write data.
11 -wire[31:0] reg_writedata; // data that will be written in the register.
12 -wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
13 -
14 -wire[31:0] alu_input2; // input data of ALU.
15 -wire[31:0] alu_result; // result data of ALU.
16 -wire alu_branch; // indicator for branch operation.
17 -
18 -wire[31:0] mem_readdata; // data from the requested address.
19 -
20 -wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg;
21 -wire[3:0] ctrl_aluctrl; // control signals.
22 -
23 -wire[31:0] extend_output;
24 -
25 -wire[31:0] shiftBranch_output;
26 -wire[31:0] shiftJump_output;
27 -
28 -Clock clock(clk);
29 -InstructionMemory instrmem(instr_address, instr);
30 -Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
31 -ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
32 -DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
33 -Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
34 -Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
35 -Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
36 -Mux32bit mux_memtoreg(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
37 -Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch);
38 -Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
39 -Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
40 -SignExtend extend(instr[15:0], extend_output);
41 -Adder add_pc4(PC, 32'h00000004, addPC4);
42 -Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
43 -ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
44 -ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
45 -
46 -initial begin
47 - PC = 32'h00000000;
48 -end
49 -
50 -always @(posedge clk) begin
51 - case(nextPC[31]) // if nextPC is available, PC = nextPC.
52 - 1'b0: PC = nextPC;
53 - 1'b1: PC = nextPC;
54 - endcase
55 -
56 - instr_address = PC;
57 -end
58 -
59 -/*
60 -wire clk; // clock
61 -reg[31:0] PC, nextPC; // program counter
62 -
63 -// Instruction Memory (IM)
64 -reg[31:0] address; // instruction address. input of IM.
65 -wire[31:0] instr; // loaded instruction. output of IM
66 -
67 -// Register
68 -reg[4:0] reg_readreg1, reg_readreg2; // register numbers of the read data. input of register.
69 -reg[4:0] reg_writereg1; // register number for the write data. input of register.
70 -reg[31:0] reg_writedata; // data that will be written in the register. input of register.
71 -reg reg_sig_regwrite; // regwrite control signal. input of register
72 -wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. outputs of register.
73 -
74 -// ALU
75 -reg[31:0] alu_input1, alu_input2; // input data of ALU. inputs of ALU.
76 -reg[3:0] alu_control; // ALU control signal. input of ALU.
77 -wire[31:0] alu_result; // result data of ALU. output of ALU.
78 -wire alu_branch; // indicator for branch operation. output of ALU.
79 -
80 -//Data Memory (DM)
81 -reg[31:0] mem_addr; // address of the read data. input of DM.
82 -reg[31:0] mem_writedata; // data that will be written in the memory. input of DM.
83 -reg mem_memread, mem_memwrite; // control signals for DM. input of DM.
84 -wire[31:0] mem_readdata; // data from the requested address. output of DM.
85 -
86 -// Control Unit
87 -reg[5:0] ctrl_opcode; // opcode of the instruction. input of control unit.
88 -wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread; // ??
89 -wire ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump; // ??? control signals outputs of control unit.
90 -wire[1:0] ctrl_aluop; // ??
91 -
92 -// ALU Control Unit
93 -reg[5:0] aluctrl_funct; // function code of the R type instructions. input of ALU control unit.
94 -reg[1:0] aluctrl_aluop; // aluop signal. input of ALU control unit.
95 -wire[3:0] aluctrl_sig; // alu control signal. output of ALU control unit.
96 -
97 -// Multiplexer (Mux)
98 - // mux_writereg Mux for Write Register.
99 -reg[4:0] mux_writereg_input1, mux_writereg_input2;
100 -reg mux_writereg_signal;
101 -wire[4:0] mux_writereg_output;
102 - // mux_alu Mux for ALU input 2.
103 -reg[31:0] mux_alu_input1, mux_alu_input2;
104 -reg mux_alu_signal;
105 -wire[31:0] mux_alu_output;
106 - // mux_writedata Mux for Write Data of Register.
107 -reg[31:0] mux_writedata_input1, mux_writedata_input2;
108 -reg mux_writedata_signal;
109 -wire[31:0] mux_writedata_output;
110 - // mux_branch Mux for Branch
111 -reg[31:0] mux_branch_input1, mux_branch_input2;
112 -reg mux_branch_signal;
113 -wire[31:0] mux_branch_output;
114 - // mux_jump Mux for Jump
115 -reg[31:0] mux_jump_input1, mux_jump_input2;
116 -reg mux_jump_signal;
117 -wire[31:0] mux_jump_output;
118 -
119 -// Sign Extend
120 -reg[15:0] extend_input;
121 -wire[31:0] extend_output;
122 -
123 -// Adder
124 - // add_pc4
125 -reg[31:0] add_pc4_input; // input2 is 4.
126 -wire[31:0] add_pc4_output;
127 - // add_branch
128 -reg[31:0] add_branch_input1, add_branch_input2;
129 -wire[31:0] add_branch_output;
130 -
131 -// Shift Left 2
132 - // shiftBranch ShiftLeft2 which is used for Branch instructions.
133 -reg[31:0] shiftBranch_input;
134 -wire[31:0] shiftBranch_output;
135 - // shiftJump ShiftLeft2 which is used for Jump instructions.
136 -reg[31:0] shiftJump_input;
137 -wire[31:0] shiftJump_output;
138 -
139 -
140 -Clock clock(clk);
141 -InstructionMemory instrmem(address, instr);
142 -Register register(reg_readreg1, reg_readreg2, reg_writereg1, reg_writedata, reg_sig_regwrite, reg_readdata1, reg_readdata2);
143 -ALU alu(alu_input1, alu_input2, alu_control, alu_result, alu_branch);
144 -DataMemory datamem(mem_addr, mem_writedata, mem_memread, mem_memwrite, mem_readdata);
145 -Control ctrl(ctrl_opcode, ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
146 -ALUControl aluctrl(aluctrl_funct, aluctrl_aluop, aluctrl_sig);
147 -Mux5bit mux_writereg(mux_writereg_input1, mux_writereg_input2, mux_writereg_signal, mux_writereg_output);
148 -Mux32bit mux_alu(mux_alu_input1, mux_alu_input2, mux_alu_signal, mux_alu_output);
149 -Mux32bit mux_writedata(mux_writedata_input1, mux_writedata_input2, mux_writedata_signal, mux_writedata_output);
150 -Mux32bit mux_branch(mux_branch_input1, mux_branch_input2, mux_branch_signal, mux_branch_output);
151 -Mux32bit mux_jump(mux_jump_input1, mux_jump_input2, mux_jump_signal, mux_jump_output);
152 -SignExtend extend(extend_input, extend_output);
153 -Adder add_pc4(add_pc4_input, 32'h00000004, add_pc4_output);
154 -Adder add_branch(add_branch_input1, add_branch_input2, add_branch_output);
155 -ShiftLeft2 shiftBranch(shiftBranch_input, shiftBranch_output);
156 -ShiftLeft2 shiftJump(shiftJump_input, shiftJump_output);
157 -
158 -initial begin
159 - PC = 32'h00000000;
160 - nextPC = 32'h00000000;
161 -end
162 -
163 -always @(posedge clk) begin
164 -// IF
165 - case(nextPC[0])
166 - 1'b0: PC = nextPC;
167 - 1'b1: PC = nextPC;
168 - endcase
169 -#1;
170 - address = PC;
171 - add_pc4_input = PC;
172 -#1;
173 -// ID
174 - ctrl_opcode <= instr[31:26];
175 - reg_readreg1 <= instr[25:21];
176 - reg_readreg2 <= instr[20:16];
177 - mux_writereg_input1 <= instr[20:16];
178 - mux_writereg_input2 <= instr[15:11];
179 - extend_input <= instr[15:0];
180 - aluctrl_funct <= instr[5:0];
181 - shiftJump_input <= {6'b000000, instr[25:0]};
182 -#1;
183 - mux_writereg_signal <= ctrl_regdst;
184 - aluctrl_aluop <= ctrl_aluop;
185 -
186 -// EX
187 - mux_alu_input1 <= reg_readdata2;
188 - mux_alu_input2 <= extend_output;
189 - mux_alu_signal <= ctrl_alusrc;
190 - shiftBranch_input <= extend_output;
191 -#1;
192 - alu_input1 <= reg_readdata1;
193 - alu_input2 <= mux_alu_output;
194 - alu_control <= aluctrl_sig;
195 - add_branch_input1 <= add_pc4_output;
196 - add_branch_input2 <= shiftBranch_output;
197 -#1;
198 - mux_branch_input1 <= add_pc4_output;
199 - mux_branch_input2 <= add_branch_output;
200 - mux_branch_signal <= ctrl_branch & alu_branch;
201 -#1;
202 -
203 -// MEM
204 - mux_jump_input1 <= mux_branch_output;
205 - mux_jump_input2 <= {add_pc4_output[31:28], shiftJump_output[27:0]};
206 - mux_jump_signal <= ctrl_jump;
207 - mem_addr <= alu_result;
208 - mem_writedata <= reg_readdata2;
209 - mem_memread <= ctrl_memread;
210 - mem_memwrite <= ctrl_memwrite;
211 -#1;
212 -// WB
213 - mux_writedata_input1 <= alu_result;
214 - mux_writedata_input2 <= mem_readdata;
215 - mux_writedata_signal <= ctrl_memtoreg;
216 -#1;
217 - reg_sig_regwrite <= ctrl_regwrite;
218 - reg_writereg1 <= mux_writereg_output;
219 - reg_writedata <= mux_writedata_output;
220 -#1;
221 - nextPC <= mux_jump_output;
222 -end
223 -*/
224 -endmodule
1 +# Reading C:/Modeltech_pe_edu_10.4a/tcl/vsim/pref.tcl
2 +# OpenFile D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
No preview for this file type
...@@ -9,7 +9,7 @@ z2 ...@@ -9,7 +9,7 @@ z2
9 cModel Technology 9 cModel Technology
10 dC:/Modeltech_pe_edu_10.4a/examples 10 dC:/Modeltech_pe_edu_10.4a/examples
11 vAdder 11 vAdder
12 -Z0 !s110 1592320284 12 +Z0 !s110 1592748174
13 !i10b 1 13 !i10b 1
14 !s100 LKl?GBS:oo[A[hLP0Qb^_1 14 !s100 LKl?GBS:oo[A[hLP0Qb^_1
15 IlbJEP?2C3Ya>zhzD12^S]1 15 IlbJEP?2C3Ya>zhzD12^S]1
...@@ -23,7 +23,7 @@ Z4 OP;L;10.4a;61 ...@@ -23,7 +23,7 @@ Z4 OP;L;10.4a;61
23 r1 23 r1
24 !s85 0 24 !s85 0
25 31 25 31
26 -Z5 !s108 1592320284.000000 26 +Z5 !s108 1592748173.000000
27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
29 !s101 -O0 29 !s101 -O0
...@@ -45,7 +45,7 @@ R4 ...@@ -45,7 +45,7 @@ R4
45 r1 45 r1
46 !s85 0 46 !s85 0
47 31 47 31
48 -R5 48 +Z7 !s108 1592748174.000000
49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
51 !s101 -O0 51 !s101 -O0
...@@ -53,7 +53,7 @@ R5 ...@@ -53,7 +53,7 @@ R5
53 R6 53 R6
54 n@a@l@u 54 n@a@l@u
55 vClock 55 vClock
56 -Z7 !s110 1592320593 56 +R0
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...@@ -67,15 +67,15 @@ R4 ...@@ -67,15 +67,15 @@ R4
67 r1 67 r1
68 !s85 0 68 !s85 0
69 31 69 31
70 -Z11 !s108 1592320593.000000 70 +R7
71 -Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v| 71 +Z11 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
72 -Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v| 72 +Z12 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
73 !s101 -O0 73 !s101 -O0
74 !i113 1 74 !i113 1
75 R6 75 R6
76 n@clock 76 n@clock
77 vClock_pipeline 77 vClock_pipeline
78 -R7 78 +R0
79 !i10b 1 79 !i10b 1
80 !s100 =@aPTZQSFah27j5MeG_d62 80 !s100 =@aPTZQSFah27j5MeG_d62
81 I8]3=4M<>=TGn3hX;LeQ183 81 I8]3=4M<>=TGn3hX;LeQ183
...@@ -89,15 +89,15 @@ R4 ...@@ -89,15 +89,15 @@ R4
89 r1 89 r1
90 !s85 0 90 !s85 0
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92 +R7
92 R11 93 R11
93 R12 94 R12
94 -R13
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97 R6 97 R6
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99 vControl 99 vControl
100 -Z14 !s110 1592320285 100 +R0
101 !i10b 1 101 !i10b 1
102 !s100 PKg@cjO2lUjfUI`iaE9QB2 102 !s100 PKg@cjO2lUjfUI`iaE9QB2
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...@@ -111,7 +111,7 @@ R4 ...@@ -111,7 +111,7 @@ R4
111 r1 111 r1
112 !s85 0 112 !s85 0
113 31 113 31
114 -Z15 !s108 1592320285.000000 114 +R7
115 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 115 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
117 !s101 -O0 117 !s101 -O0
...@@ -119,7 +119,7 @@ Z15 !s108 1592320285.000000 ...@@ -119,7 +119,7 @@ Z15 !s108 1592320285.000000
119 R6 119 R6
120 n@control 120 n@control
121 vDataMemory 121 vDataMemory
122 -R14 122 +R0
123 !i10b 1 123 !i10b 1
124 !s100 e=5E[GS05J<RCdT=KSMX_1 124 !s100 e=5E[GS05J<RCdT=KSMX_1
125 I9=L>R4ccfGY8^T;U50LY?1 125 I9=L>R4ccfGY8^T;U50LY?1
...@@ -133,7 +133,7 @@ R4 ...@@ -133,7 +133,7 @@ R4
133 r1 133 r1
134 !s85 0 134 !s85 0
135 31 135 31
136 -R15 136 +R7
137 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 137 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
138 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 138 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
139 !s101 -O0 139 !s101 -O0
...@@ -141,123 +141,123 @@ R15 ...@@ -141,123 +141,123 @@ R15
141 R6 141 R6
142 n@data@memory 142 n@data@memory
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144 -Z16 !s110 1592320286 144 +Z13 !s110 1592748176
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146 !s100 k5Dc_]iZ1_]4AXAj8[5Y<1 146 !s100 k5Dc_]iZ1_]4AXAj8[5Y<1
147 IeKKdJcFcgGh?YcYVb3j^N0 147 IeKKdJcFcgGh?YcYVb3j^N0
148 R1 148 R1
149 R2 149 R2
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151 -Z18 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 151 +Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
152 -Z19 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 152 +Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
153 L0 123 153 L0 123
154 R4 154 R4
155 r1 155 r1
156 !s85 0 156 !s85 0
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158 -Z20 !s108 1592320286.000000 158 +Z17 !s108 1592748176.000000
159 -Z21 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 159 +Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
160 -Z22 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 160 +Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
161 !s101 -O0 161 !s101 -O0
162 !i113 1 162 !i113 1
163 R6 163 R6
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165 vHazardHandling 165 vHazardHandling
166 -R14 166 +Z20 !s110 1592748175
167 !i10b 1 167 !i10b 1
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170 R1 170 R1
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172 -Z23 w1592320280 172 +Z21 w1592320280
173 -Z24 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 173 +Z22 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
174 -Z25 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v 174 +Z23 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
175 L0 2 175 L0 2
176 R4 176 R4
177 r1 177 r1
178 !s85 0 178 !s85 0
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181 -Z26 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v| 181 +Z25 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
182 -Z27 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v| 182 +Z26 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
183 !s101 -O0 183 !s101 -O0
184 !i113 1 184 !i113 1
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188 -R14 188 +R20
189 !i10b 1 189 !i10b 1
190 !s100 7f=OHLAZQeViCagN[c9Sf3 190 !s100 7f=OHLAZQeViCagN[c9Sf3
191 IZ44zQQI;2gGiN8L`RbQ<=1 191 IZ44zQQI;2gGiN8L`RbQ<=1
192 R1 192 R1
193 R2 193 R2
194 +R21
195 +R22
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195 -R24
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214 R1 214 R1
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220 R4 220 R4
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228 !i113 1 228 !i113 1
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230 n@i@d_@e@x 230 n@i@d_@e@x
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232 -R16 232 +R13
233 !i10b 1 233 !i10b 1
234 !s100 bKKM:?Mi3;B]TOe]O7<e>3 234 !s100 bKKM:?Mi3;B]TOe]O7<e>3
235 I[FaS1INGbXUlELb9411?G2 235 I[FaS1INGbXUlELb9411?G2
236 R1 236 R1
237 R2 237 R2
238 -R17 238 +R14
239 -R18 239 +R15
240 -R19 240 +R16
241 L0 27 241 L0 27
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243 r1 243 r1
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256 -!s100 5C;cU;MQ6jR<THFX]C[C_0 256 +!s100 E683aVzbm`;9giCYOIXB@0
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262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
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...@@ -265,7 +265,7 @@ R4 ...@@ -265,7 +265,7 @@ R4
265 r1 265 r1
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269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
271 !s101 -O0 271 !s101 -O0
...@@ -273,29 +273,29 @@ r1 ...@@ -273,29 +273,29 @@ r1
273 R6 273 R6
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276 -R16 276 +R13
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280 R1 280 R1
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292 -R22 292 +R19
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294 !i113 1 294 !i113 1
295 R6 295 R6
296 n@m@e@m_@w@b 296 n@m@e@m_@w@b
297 vMIPS_Pipeline 297 vMIPS_Pipeline
298 -R16 298 +R20
299 !i10b 1 299 !i10b 1
300 !s100 =YiG<BP8;FThR9<Of:]<42 300 !s100 =YiG<BP8;FThR9<Of:]<42
301 Iz:PlBdl:5iijJ8LoFBAOe1 301 Iz:PlBdl:5iijJ8LoFBAOe1
...@@ -309,7 +309,7 @@ R4 ...@@ -309,7 +309,7 @@ R4
309 r1 309 r1
310 !s85 0 310 !s85 0
311 31 311 31
312 -R15 312 +R24
313 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 313 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
314 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 314 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
315 !s101 -O0 315 !s101 -O0
...@@ -317,7 +317,7 @@ R15 ...@@ -317,7 +317,7 @@ R15
317 R6 317 R6
318 n@m@i@p@s_@pipeline 318 n@m@i@p@s_@pipeline
319 vMIPS_Pipeline_Forwarding 319 vMIPS_Pipeline_Forwarding
320 -R16 320 +R20
321 !i10b 1 321 !i10b 1
322 !s100 0[k6421_Q:5fJX9:k0cCE0 322 !s100 0[k6421_Q:5fJX9:k0cCE0
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...@@ -331,7 +331,7 @@ R4 ...@@ -331,7 +331,7 @@ R4
331 r1 331 r1
332 !s85 0 332 !s85 0
333 31 333 31
334 -R20 334 +R24
335 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v| 335 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
336 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v| 336 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
337 !s101 -O0 337 !s101 -O0
...@@ -339,7 +339,7 @@ R20 ...@@ -339,7 +339,7 @@ R20
339 R6 339 R6
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342 -R16 342 +R13
343 !i10b 1 343 !i10b 1
344 !s100 gM[;Cl]DhJhX67JceN9VX0 344 !s100 gM[;Cl]DhJhX67JceN9VX0
345 IEZ2gnb65W:EYTLgmRHR8f2 345 IEZ2gnb65W:EYTLgmRHR8f2
...@@ -353,7 +353,7 @@ R4 ...@@ -353,7 +353,7 @@ R4
353 r1 353 r1
354 !s85 0 354 !s85 0
355 31 355 31
356 -R20 356 +R24
357 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 357 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
358 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 358 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
359 !s101 -O0 359 !s101 -O0
...@@ -361,123 +361,123 @@ R20 ...@@ -361,123 +361,123 @@ R20
361 R6 361 R6
362 n@m@i@p@s_@single@cycle 362 n@m@i@p@s_@single@cycle
363 vMux32bit 363 vMux32bit
364 -R16 364 +R13
365 !i10b 1 365 !i10b 1
366 !s100 foJG^YU75_eND1Og;6Z>O1 366 !s100 foJG^YU75_eND1Og;6Z>O1
367 II3=gjhQD0_cn8mlDL]@bi1 367 II3=gjhQD0_cn8mlDL]@bi1
368 R1 368 R1
369 R2 369 R2
370 -R17 370 +R14
371 -Z28 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 371 +Z27 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
372 -Z29 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 372 +Z28 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
373 L0 15 373 L0 15
374 R4 374 R4
375 r1 375 r1
376 !s85 0 376 !s85 0
377 31 377 31
378 -R20 378 +R17
379 -Z30 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 379 +Z29 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
380 -Z31 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 380 +Z30 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
381 !s101 -O0 381 !s101 -O0
382 !i113 1 382 !i113 1
383 R6 383 R6
384 n@mux32bit 384 n@mux32bit
385 vMux5bit 385 vMux5bit
386 -R16 386 +R13
387 !i10b 1 387 !i10b 1
388 !s100 oSd=[kHDJb<:G7LN4]6@e3 388 !s100 oSd=[kHDJb<:G7LN4]6@e3
389 IfiVXg_aB2GQG7?F@=HcEi0 389 IfiVXg_aB2GQG7?F@=HcEi0
390 R1 390 R1
391 R2 391 R2
392 -R17 392 +R14
393 +R27
393 R28 394 R28
394 -R29
395 L0 1 395 L0 1
396 R4 396 R4
397 r1 397 r1
398 !s85 0 398 !s85 0
399 31 399 31
400 -R20 400 +R17
401 +R29
401 R30 402 R30
402 -R31
403 !s101 -O0 403 !s101 -O0
404 !i113 1 404 !i113 1
405 R6 405 R6
406 n@mux5bit 406 n@mux5bit
407 vMux_Forwarding 407 vMux_Forwarding
408 -R14 408 +R20
409 !i10b 1 409 !i10b 1
410 !s100 iCag5di1L;N5IB81hdLH>2 410 !s100 iCag5di1L;N5IB81hdLH>2
411 I:XNmLIF]Ed49A_PQCSjO=0 411 I:XNmLIF]Ed49A_PQCSjO=0
412 R1 412 R1
413 R2 413 R2
414 +R21
415 +R22
414 R23 416 R23
415 -R24
416 -R25
417 L0 159 417 L0 159
418 R4 418 R4
419 r1 419 r1
420 !s85 0 420 !s85 0
421 31 421 31
422 -R15 422 +R24
423 +R25
423 R26 424 R26
424 -R27
425 !s101 -O0 425 !s101 -O0
426 !i113 1 426 !i113 1
427 R6 427 R6
428 n@mux_@forwarding 428 n@mux_@forwarding
429 vMuxBranchSignal 429 vMuxBranchSignal
430 -R16 430 +R13
431 !i10b 1 431 !i10b 1
432 !s100 H1RKS9h`Y6QFX88CRc<g[0 432 !s100 H1RKS9h`Y6QFX88CRc<g[0
433 IGJT?gXMKEEWH?G^lPN79V2 433 IGJT?gXMKEEWH?G^lPN79V2
434 R1 434 R1
435 R2 435 R2
436 -R17 436 +R14
437 +R27
437 R28 438 R28
438 -R29
439 L0 29 439 L0 29
440 R4 440 R4
441 r1 441 r1
442 !s85 0 442 !s85 0
443 31 443 31
444 -R20 444 +R17
445 +R29
445 R30 446 R30
446 -R31
447 !s101 -O0 447 !s101 -O0
448 !i113 1 448 !i113 1
449 R6 449 R6
450 n@mux@branch@signal 450 n@mux@branch@signal
451 vPCregister 451 vPCregister
452 -R16 452 +R13
453 !i10b 1 453 !i10b 1
454 !s100 ZWKU[XiaKQUFo0lg:i>8J3 454 !s100 ZWKU[XiaKQUFo0lg:i>8J3
455 IJN5hl<_id]kA5B6k4:9oE1 455 IJN5hl<_id]kA5B6k4:9oE1
456 R1 456 R1
457 R2 457 R2
458 -R17 458 +R14
459 -R18 459 +R15
460 -R19 460 +R16
461 L0 1 461 L0 1
462 R4 462 R4
463 r1 463 r1
464 !s85 0 464 !s85 0
465 31 465 31
466 -R20 466 +R17
467 -R21 467 +R18
468 -R22 468 +R19
469 !s101 -O0 469 !s101 -O0
470 !i113 1 470 !i113 1
471 R6 471 R6
472 n@p@cregister 472 n@p@cregister
473 vRegister 473 vRegister
474 -Z32 !s110 1592320287 474 +R13
475 !i10b 1 475 !i10b 1
476 !s100 bC`<7GaPg=bDaZoUR<ADa0 476 !s100 bC`<7GaPg=bDaZoUR<ADa0
477 I<aR5RJ2c1Qba>GdC]KZCd2 477 I<aR5RJ2c1Qba>GdC]KZCd2
478 R1 478 R1
479 R2 479 R2
480 -R17 480 +R14
481 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 481 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
482 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v 482 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
483 L0 1 483 L0 1
...@@ -485,7 +485,7 @@ R4 ...@@ -485,7 +485,7 @@ R4
485 r1 485 r1
486 !s85 0 486 !s85 0
487 31 487 31
488 -Z33 !s108 1592320287.000000 488 +R17
489 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 489 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
490 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 490 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
491 !s101 -O0 491 !s101 -O0
...@@ -493,13 +493,13 @@ Z33 !s108 1592320287.000000 ...@@ -493,13 +493,13 @@ Z33 !s108 1592320287.000000
493 R6 493 R6
494 n@register 494 n@register
495 vShiftLeft2 495 vShiftLeft2
496 -R32 496 +R13
497 !i10b 1 497 !i10b 1
498 !s100 ]Zje9D[f?jFRnJBn`OeHc1 498 !s100 ]Zje9D[f?jFRnJBn`OeHc1
499 I]0TYJ]_7?FkOoY=2GlT5=3 499 I]0TYJ]_7?FkOoY=2GlT5=3
500 R1 500 R1
501 R2 501 R2
502 -R17 502 +R14
503 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 503 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
504 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v 504 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
505 L0 1 505 L0 1
...@@ -507,7 +507,7 @@ R4 ...@@ -507,7 +507,7 @@ R4
507 r1 507 r1
508 !s85 0 508 !s85 0
509 31 509 31
510 -R33 510 +R17
511 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 511 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
512 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 512 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
513 !s101 -O0 513 !s101 -O0
...@@ -515,13 +515,13 @@ R33 ...@@ -515,13 +515,13 @@ R33
515 R6 515 R6
516 n@shift@left2 516 n@shift@left2
517 vSignExtend 517 vSignExtend
518 -R0 518 +!s110 1592748173
519 !i10b 1 519 !i10b 1
520 !s100 =4eXcc0im3]S=Kk@o:eh32 520 !s100 =4eXcc0im3]S=Kk@o:eh32
521 IFBiMm>fY8WE23A[Ye;CUj3 521 IFBiMm>fY8WE23A[Ye;CUj3
522 R1 522 R1
523 R2 523 R2
524 -R17 524 +R14
525 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 525 8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
526 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 526 FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
527 L0 1 527 L0 1
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