Hazard 관리 기능 수정, Forwarding 방식 추가 및 오류 수정

@@ -38,7 +38,7 @@ always @(*) begin
 				6'b001000: begin		//  jr
 			//		regdst = 1'bz;
 					regwrite = 1'b0;
-			//		alusrc = 1'bz;
+					alusrc = 1'b1;
 					aluctrl = 4'b1111;
 				//	memread = 1'b0;
 				//	memwrite = 1'b0;
@@ -51,7 +51,7 @@ always @(*) begin
 				default: begin
 			//		regdst = 1'bz;
 					regwrite = 1'b0;
-			//		alusrc = 1'bz;
+					alusrc = 1'b1;
 					aluctrl = 4'b1111;
 				//	memread = 1'b0;
 				//	memwrite = 1'b0;
@@ -222,7 +222,7 @@ always @(*) begin
 		6'b000010: begin		// jump instruction
 		//	regdst = 1'bz;
 			regwrite = 1'b0;
-		//	alusrc = 1'bz;
+			alusrc = 1'b1;
 			aluctrl = 4'b1111;
 			memread = 1'b0;
 			memwrite = 1'b0;
@@ -236,7 +236,7 @@ always @(*) begin
 		6'b000011: begin		// jal instruction
 		//	regdst = 1'bz;
 			regwrite = 1'b1;
-		//	alusrc = 1'bz;
+			alusrc = 1'b1;
 			aluctrl = 4'b1111;
 			memread = 1'b0;
 			memwrite = 1'b0;
@@ -278,7 +278,7 @@ always @(*) begin
 		default: begin			// unknown instruction
 		//	regdst = 1'bz;
 			regwrite = 1'b0;
-		//	alusrc = 1'bz;
+			alusrc = 1'b1;
 			aluctrl = 4'b1111;
 			memread = 1'b0;
 			memwrite = 1'b0;

-// Data Hazard Handling
-module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 
-	in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 
-	out_stallsignal);
+// Hazard Handling ( No Fowarding )
+module HazardHandling(clk, 
+	in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 									// for data hazard handling
+	in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 						
+	in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch, in_wb_nextPC, 										// for control hazard handling
+	out_stallsignal, out_flushsignal, out_nextPC);
 input clk;
-input in_ex_regwrite, in_mem_regwrite, in_wb_regwrite;
-input[4:0] in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
+input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_id_jump, in_ex_branch, in_wb_jump, in_wb_branch;
+input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
+input[31:0] in_wb_nextPC;
+
 output reg out_stallsignal;
+output reg[4:0] out_flushsignal;
+output reg[31:0] out_nextPC;
 
-initial out_stallsignal = 1'b0;
+reg[4:0] readreg2;
 
+initial begin
+	readreg2 <= 5'b00000;
+	out_stallsignal <= 1'b0;
+	out_flushsignal <= 5'b00000;
+	out_nextPC <= 32'h00000000;
+end
 always @(negedge clk) begin
-	if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_readreg_num1 || in_ex_writereg_num==in_readreg_num2)) begin
+// Data Hazard Handling
+	readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
+	if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2)) begin
 		out_stallsignal = 1'b1;
-	end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_readreg_num1 || in_mem_writereg_num==in_readreg_num2)) begin
+		out_flushsignal = 5'b00100;
+	end else if((in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000) && (in_mem_writereg_num==in_id_readreg_num1 || in_mem_writereg_num==readreg2)) begin
 		out_stallsignal = 1'b1;
-	end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_readreg_num1 || in_wb_writereg_num==in_readreg_num2)) begin
+		out_flushsignal = 5'b00100;
+	end else if((in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000) && (in_wb_writereg_num==in_id_readreg_num1 || in_wb_writereg_num==readreg2)) begin
+		out_stallsignal = 1'b1;	
+		out_flushsignal = 5'b00100;
+	end else begin
+		out_stallsignal = 1'b0;
+
+// Control Hazard Handling
+		if(in_id_jump == 1'b1) out_flushsignal = 5'b11000;
+		else if(in_ex_branch == 1'b1) out_flushsignal = 5'b11100;
+		else if(in_wb_jump==1'b1 || in_wb_branch==1'b1) begin
+			out_nextPC = in_wb_nextPC;
+			out_flushsignal[4] = 1'b0;
+		end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
+	end
+end
+endmodule
+
+
+// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
+// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
+// ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
+
+
+// Hazard Handling ( Fowarding )
+// not finished
+module HazardHandling_Forwarding(clk, 
+	in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_ex_memtoreg, 							// for data hazard handling
+	in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 
+	in_id_jump, in_id_jumpreg, in_ex_jumpreg, in_ex_branch, 				 							// for control hazard handling
+	in_id_PCjump, in_ex_PCjumpreg, in_ex_PCbranch, 
+	out_stallsignal, out_flushsignal, out_fowardsig1, out_fowardsig2, out_nextPC);
+input clk;
+input in_id_alusrc, in_id_memwrite, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, in_ex_memtoreg, in_id_jump, in_id_jumpreg, in_ex_jumpreg, in_ex_branch;
+input[4:0] in_id_readreg_num1, in_id_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num;
+input[31:0] in_id_PCjump, in_ex_PCjumpreg, in_ex_PCbranch;
+
+output reg out_stallsignal;
+output reg[1:0] out_fowardsig1, out_fowardsig2;
+output reg[4:0] out_flushsignal;
+output reg[31:0] out_nextPC;
+
+reg branchfinished;
+reg[4:0] readreg2;
+
+initial begin
+	branchfinished = 1'b0;
+	readreg2 = 5'b00000;
+	out_stallsignal = 1'b0;
+	out_flushsignal = 5'b00000;
+	out_fowardsig1 = 2'b00;
+	out_fowardsig2 = 2'b00;
+	out_nextPC = 32'h00000000;
+end
+always @(negedge clk) begin
+// Data Hazard Handling
+	readreg2 = (in_id_alusrc==1'b1 && in_id_memwrite==1'b0) ? 5'b00000 : in_id_readreg_num2;
+	if((in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000) && (in_ex_writereg_num==in_id_readreg_num1 || in_ex_writereg_num==readreg2) && in_ex_memtoreg==1'b1) begin
 		out_stallsignal = 1'b1;
-	end else out_stallsignal = 1'b0;
+		out_flushsignal = 5'b00100;
+	end else begin
+		if(in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000 && in_ex_writereg_num==in_id_readreg_num1 && in_ex_memtoreg==1'b0) out_fowardsig1 = 2'b01;
+		else if(in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000 && in_mem_writereg_num==in_id_readreg_num1) out_fowardsig1 = 2'b10;
+		else if(in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000 && in_wb_writereg_num==in_id_readreg_num1) out_fowardsig1 = 2'b11;
+		else out_fowardsig1 = 2'b00;
+
+		if(in_ex_regwrite==1'b1 && in_ex_writereg_num!=5'b00000 && in_ex_writereg_num==readreg2 && in_ex_memtoreg==1'b0) out_fowardsig2 = 2'b01;
+		else if(in_mem_regwrite==1'b1 && in_mem_writereg_num!=5'b00000 && in_mem_writereg_num==readreg2) out_fowardsig2 = 2'b10;
+		else if(in_wb_regwrite==1'b1 && in_wb_writereg_num!=5'b00000 && in_wb_writereg_num==readreg2) out_fowardsig2 = 2'b11;
+		else out_fowardsig2 = 2'b00;
+
+// Control Hazard Handling
+		if(branchfinished == 1'b1) begin
+			out_flushsignal[4] = 1'b0;
+			branchfinished = 1'b0;
+		end else if(in_id_jump == 1'b1 && in_id_jumpreg == 1'b0) begin
+			out_nextPC = in_id_PCjump;
+			out_flushsignal = 5'b11000;
+			branchfinished = 1'b1;
+		end else if(in_ex_jumpreg == 1'b1) begin
+			out_nextPC = in_ex_PCjumpreg;
+			out_flushsignal = 5'b11100;
+			branchfinished = 1'b1;
+		end else if(in_ex_branch == 1'b1) begin
+			out_nextPC = in_ex_PCbranch;
+			out_flushsignal = 5'b11100;
+			branchfinished = 1'b1;
+		end else if(out_flushsignal[4] == 1'b0) out_flushsignal = 5'b00000;
+	end
 end
+endmodule
+
+module Mux_Forwarding(input1, input2, input3, input4, signal, output1);
+input[31:0] input1, input2, input3, input4;
+input[1:0] signal;
+output reg[31:0] output1;
 
+always @(*) begin
+	case(signal)
+		2'b00: output1 <= input1;
+		2'b01: output1 <= input2;
+		2'b10: output1 <= input3;
+		2'b11: output1 <= input4;
+	endcase
+end
 endmodule
 
 
+
+
 // Control Hazard Handling
-module Flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch, 
-	out_flush_jump, out_flush_branch, out_pc);
+/*
+module Flush_fowarding(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch, 
+	out_flush, out_pc);
 input clk;
 
 input ctrl_jump, ctrl_jumpreg, ex_branchsignal;
 input[2:0] ctrl_branch;
 input[31:0] pc_jump, pc_jumpreg, ex_pc_branch;
 
-output reg out_flush_jump, out_flush_branch;
+output reg[4:0] out_flush;
 output reg[31:0] out_pc;
 
 reg isbranch;
 
 initial begin
 	isbranch = 1'b0;
-	out_flush_jump = 1'b0;
-	out_flush_branch = 1'b0;
+	out_flush = 5'b00000;
 	out_pc = 32'h00000000;
 end
 
@@ -47,17 +164,16 @@ always @(negedge clk) begin
 	if(isbranch == 1'b1) begin
 		if(ex_branchsignal == 1'b1) begin
 			out_pc = ex_pc_branch;
-			out_flush_branch = 1'b1;
+			out_flush = 5'b11100;
 		end 
 		isbranch = 1'b0;
 	end else begin
-		out_flush_branch = 1'b0;
-
 		if(ctrl_jump == 1'b1) begin
-			out_flush_jump = 1'b1;
+			out_flush = 5'b11000;
 			out_pc = (ctrl_jumpreg == 1'b0) ? pc_jump : pc_jumpreg;
 		end else if(ctrl_branch != 3'b000) isbranch = 1'b1;
-		else out_flush_jump = 1'b0;
+		else out_flush = 5'b00000;
 	end
 end
 endmodule
+*/
\ No newline at end of file

@@ -6,37 +6,48 @@ output reg[31:0] instruction;
 reg[31:0] instr_mem[127:0];
 /*
 initial begin
+
+end
+*/
+/*
+initial begin
 instr_mem[0] = 32'd0;
 instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
-instr_mem[2] = 32'd0;
-instr_mem[3] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[3] = 32'b00100101101011010000000000000011;		// addi, $13 $13 3
 instr_mem[4] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
-instr_mem[5] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
-instr_mem[6] = 32'b00100100000011010000000000000011;		// addi, $0 $13 3
-instr_mem[7] = 32'b00100100000010010000000000000001;		// addi, $0 $9 1
-instr_mem[8] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
+instr_mem[5] = 32'd0;
+instr_mem[6] = 32'b00100101101011010000000000000011;		// addi, $13 $13 3
+instr_mem[7] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
+instr_mem[8] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
 instr_mem[9] = 32'd0;
+instr_mem[10] = 32'b00100101101011010000000000000011;		// addi, $13 $13 3
+instr_mem[11] = 32'b00100100000010010000000000000001;		// addi, $0 $9 1
+instr_mem[12] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
+instr_mem[13] = 32'd0;
 end
 */
 
 initial begin
-instr_mem[0] = 32'd0;
+instr_mem[0] = 32'b00100111000110000000000111111111;		// addi, $24 $24 511
 instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
 instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
 instr_mem[3] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
 instr_mem[4] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
-instr_mem[5] = 32'b00010001000010100000000000000001;		// beq, $8 $10 +1
-instr_mem[6] = 32'b00000001000000000111100000100000;		// add, $8 $0 $15
-instr_mem[7] = 32'b00000001000010010000000000011000;		// mult, $8 $9
+instr_mem[5] = 32'b00010001000010100000000000000101;		// beq, $8 $10 +5
+instr_mem[6] = 32'b00000001000010010000000000011000;		// mult, $8 $9
+instr_mem[7] = 32'b00000001000000000111100000100000;		// add, $8 $0 $15
 instr_mem[8] = 32'd0;
 instr_mem[9] = 32'b00000000000000000110000000010000;		// mfhi, $12
 instr_mem[10] = 32'b00000000000000000110100000010010;		// mflo, $13
-instr_mem[11] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
+instr_mem[11] = 32'b10101100000010010000000000111100;		// sw, $0 $9 60
 instr_mem[12] = 32'd0;
 instr_mem[13] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
 instr_mem[14] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
-instr_mem[15] = 32'b00001100000000000000000000010000;		// jal, 16
-instr_mem[16] = 32'b00000000000000000000000000001000;		// jr, $0
+instr_mem[15] = 32'b00001100000000000000000000010001;		// jal, 17
+instr_mem[16] = 32'b00000001000010010000000000011000;		// mult, $8 $9
+instr_mem[17] = 32'b00000000000000000000000000001000;		// jr, $0
+instr_mem[18] = 32'b00000001000010010000000000011000;		// mult, $8 $9
 end
 
 always @ (*) begin

@@ -5,6 +5,13 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7
 Top level modules:
 	Adder
 
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module MIPS_Pipeline_Forwarding
+
+Top level modules:
+	MIPS_Pipeline_Forwarding
+
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module MIPS_SingleCycle
@@ -26,36 +33,38 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7
 Top level modules:
 	Register
 
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module MIPS_Pipeline
-
-Top level modules:
-	MIPS_Pipeline
-
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module PCregister
 -- Compiling module IF_ID
 -- Compiling module ID_EX
 -- Compiling module EX_MEM
 -- Compiling module MEM_WB
--- Compiling module PCcounter
 
 Top level modules:
+	PCregister
 	IF_ID
 	ID_EX
 	EX_MEM
 	MEM_WB
-	PCcounter
+
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
+-- Compiling module MIPS_Pipeline
+
+Top level modules:
+	MIPS_Pipeline
 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module Stall
--- Compiling module Flush
+-- Compiling module HazardHandling
+-- Compiling module HazardHandling_Forwarding
+-- Compiling module Mux_Forwarding
 
 Top level modules:
-	Stall
-	Flush
+	HazardHandling
+	HazardHandling_Forwarding
+	Mux_Forwarding
 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
@@ -106,8 +115,10 @@ Top level modules:
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Clock
+-- Compiling module Clock_pipeline
 
 Top level modules:
 	Clock
+	Clock_pipeline
 
 } {} {}}

@@ -816,7 +816,7 @@ Resolution = ns
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 100 ns
+RunLength = 100
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 10000000
@@ -2034,35 +2034,37 @@ suppress = 8780 ;an explanation can be had by running: verror 8780
 Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
-Project_Files_Count = 14
+Project_Files_Count = 15
 Project_File_0 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039528 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591976493 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591979413 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452599 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591980998 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592303982 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592102255 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592295803 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238349 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_5 = D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591982553 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591970913 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039196 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591975942 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452276 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452448 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039219 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452257 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591110854 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592266109 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592293934 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592303944 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039196 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592280009 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238365 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591452448 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1591039219 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592238359 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1592091089 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0

-// Test Required
 module MIPS_Pipeline;
-
 wire clk;
-wire stallsignal;
-wire flush_jump, flush_branch;
-wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC, flush_pc;
+wire[31:0] _PC, addPC4, addPCbranch, tempPC_branch, tempPC_jump, PC_branch, nextPC;
 
 wire[31:0] instr;						// loaded instruction.
 
@@ -44,24 +40,30 @@ wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_
 
 // MEM_WB register outputs
 wire[4:0] memwb_writereg1;
-wire memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link;
-wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch;
+wire memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link;
+wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch;
+
+// Hazard Handling Outputs
+wire stallsignal;
+wire[4:0] flushsignal;
+wire[31:0] flush_nextPC;
 
-wire temp;
-assign temp = 1'b0;
+Clock_pipeline clock(clk);
+PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
 
-Clock clock(clk);
-PCcounter pccounter(clk, stallsignal, (flush_jump|flush_branch), flush_pc, instr_address);
-Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, stallsignal);
-Flush flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, branch_signal, {ifid_PC_4[31:28], shiftJump_output[27:0]}, reg_readdata1, addPCbranch, 
-	flush_jump, flush_branch, flush_pc);
+// Hazard Handling (No Fowarding)
+HazardHandling hazardhandling(clk, 
+	ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, 				// for data hazard handling
+	ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, 
+	ctrl_jump, branch_signal, memwb_jump, memwb_branch, nextPC, 
+	stallsignal, flushsignal, flush_nextPC);
 
 // Instruction Fetch
-InstructionMemory instrmem(instr_address, instr);
-Adder add_pc4(instr_address, 32'h00000004, addPC4);
+InstructionMemory instrmem(_PC, instr);
+Adder add_pc4(_PC, 32'h00000004, addPC4);
 
-IF_ID ifid(clk, stallsignal, 
-	(flush_jump|flush_branch), instr, addPC4, 
+IF_ID ifid(clk, stallsignal, flushsignal[3], 
+	instr, addPC4, 
 	ifid_instr, ifid_PC_4);
 
 // Instruction Decode
@@ -73,7 +75,7 @@ Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, re
 SignExtend extend(ifid_instr[15:0], extend_output);
 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
 
-ID_EX idex(clk, stallsignal, flush_branch, 
+ID_EX idex(clk, flushsignal[2], 
 	reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link, 
 	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, 
 	idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link, 
@@ -87,27 +89,28 @@ Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
 MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);
 
-EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link, 
+EX_MEM ex_mem(clk, flushsignal[1], 
+	idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link, 
 	alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 
 	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 
 	exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
 
 // Memory
 DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exmem_memwrite,  mem_readdata);
-Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch,  exmem_branch ,  tempPC_branch);
 
-MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, exmem_link, 
-	exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, tempPC_branch, 
-	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link, 
-	memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch);
+MEM_WB mem_wb(clk, flushsignal[0], 
+	exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 
+	exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch, 
+	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link, 
+	memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch);
 
 // Writeback
 Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  temp_writedata);
 Mux32bit mux_link_data(temp_writedata, memwb_PC_4,  memwb_link,  reg_writedata);
-Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump,  memwb_jump,  nextPC);
+Mux32bit mux_branch(memwb_PC_4, memwb_tempPCbranch,  memwb_branch ,  PC_branch);
+Mux32bit mux_jump(PC_branch, memwb_PCjump,  memwb_jump,  nextPC);
 
 
-always @(posedge clk) begin
-end
+always @(posedge clk) begin end
 
 endmodule

+// Test Required
+module MIPS_Pipeline_Forwarding;
+wire clk;
+wire[31:0] _PC, addPC4, addPCbranch, tempPC_branch, tempPC_jump, PC_branch, nextPC;
+
+wire[31:0] instr;						// loaded instruction.
+
+wire[4:0] temp_writereg, reg_writereg1;				// register number for the write data.
+wire[31:0] temp_writedata, reg_writedata;			// data that will be written in the register.
+wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.
+
+wire[31:0] alu_input2;						// input data of ALU.
+wire[31:0] alu_result;						// result data of ALU.
+wire[5:0] alu_branch;						// indicator for branch operation.
+
+wire[31:0] mem_readdata;					// data from the requested address.
+
+wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
+wire[3:0] ctrl_aluctrl;						// control signals.
+wire[2:0] ctrl_branch;
+
+wire[31:0] extend_output;
+
+wire[31:0] shiftBranch_output;
+wire[31:0] shiftJump_output;
+
+// IF_ID register outputs
+wire[31:0] ifid_instr, ifid_PC_4;
+
+// ID_EX register outputs
+wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
+wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg, idex_link;
+wire[3:0] idex_aluctrl; 
+wire[2:0] idex_branch;
+wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;
+
+// EX_MEM register outputs
+wire[4:0] exmem_writereg1;
+wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link;
+wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;
+
+// MEM_WB register outputs
+wire[4:0] memwb_writereg1;
+wire memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link;
+wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch;
+
+// Hazard Handling Outputs
+wire stallsignal;
+wire[4:0] flushsignal;
+wire[1:0] fowardsig1, fowardsig2;
+wire[31:0] flush_nextPC;
+// Forwarding Mux Outputs
+wire[31:0] forwarding_mem_writeregdata, forwarding_id_readdata1, forwarding_id_readdata2;
+
+Clock_pipeline clock(clk);
+PCregister pcreg(clk, stallsignal, flushsignal[4], flush_nextPC, _PC);
+
+// Hazard Handling (Fowarding) not finished
+HazardHandling_Forwarding hazardhandling(clk, 
+	ctrl_alusrc, ctrl_memwrite, idex_regwrite, exmem_regwrite, memwb_regwrite, idex_memtoreg, 							// for data hazard handling
+	ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, 
+	ctrl_jump, ctrl_jumpreg, idex_jumpreg, branch_signal, 					 							// for control hazard handling
+	{ifid_PC_4[31:28], shiftJump_output[27:0]}, idex_readdata1, addPCbranch, 
+	stallsignal, flushsignal, fowardsig1, fowardsig2, flush_nextPC);
+
+
+// Instruction Fetch
+InstructionMemory instrmem(_PC, instr);
+Adder add_pc4(_PC, 32'h00000004, addPC4);
+
+IF_ID ifid(clk, stallsignal, flushsignal[3], 
+	instr, addPC4, 
+	ifid_instr, ifid_PC_4);
+
+// Instruction Decode
+Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], 
+	ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
+Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11],  ctrl_regdst,  temp_writereg);
+Mux5bit mux_link_reg(temp_writereg, 5'b11111,  ctrl_link,  reg_writereg1);
+Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata,  memwb_regwrite,  reg_readdata1, reg_readdata2);
+SignExtend extend(ifid_instr[15:0], extend_output);
+ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
+
+	// forwarding mux
+Mux32bit mux_forwarding_mem(exmem_aluresult, mem_readdata,  exmem_memtoreg,  forwarding_mem_writeregdata);
+Mux_Forwarding mux_forwrading1(reg_readdata1, alu_result, forwarding_mem_writeregdata, reg_writedata,  fowardsig1,  forwarding_id_readdata1);
+Mux_Forwarding mux_forwrading2(reg_readdata2, alu_result, forwarding_mem_writeregdata, reg_writedata,  fowardsig2,  forwarding_id_readdata2);
+
+ID_EX idex(clk, flushsignal[2], 
+	reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link, 
+	forwarding_id_readdata1, forwarding_id_readdata2, extend_output, ifid_PC_4, shiftJump_output, 
+	idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link, 
+	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
+
+// Execute
+Mux32bit mux_alusrc(idex_readdata2, idex_extenddata,  idex_alusrc,  alu_input2);
+ALU alu(clk, idex_readdata1, alu_input2,  idex_aluctrl,  alu_result, alu_branch);
+ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
+Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
+MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
+Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);
+
+EX_MEM ex_mem(clk, flushsignal[1], 
+	idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link, 
+	alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 
+	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 
+	exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
+
+// Memory
+DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exmem_memwrite,  mem_readdata);
+
+MEM_WB mem_wb(clk, flushsignal[0], 
+	exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 
+	exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch, 
+	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_branch, memwb_jump, memwb_link, 
+	memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_tempPCbranch);
+
+// Writeback
+Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  temp_writedata);
+Mux32bit mux_link_data(temp_writedata, memwb_PC_4,  memwb_link,  reg_writedata);
+Mux32bit mux_branch(memwb_PC_4, memwb_tempPCbranch,  memwb_branch ,  PC_branch);
+Mux32bit mux_jump(PC_branch, memwb_PCjump,  memwb_jump,  nextPC);
+
+
+always @(posedge clk) begin end
+
+endmodule

@@ -49,6 +49,7 @@ Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
 ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
 ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
 
+// PC Register
 initial begin
 	PC = 32'h00000000;
 end

+module PCregister(clk, stall, flush, in_pc, out_nextpc);
+input clk, stall, flush;
+
+input[31:0] in_pc;
+output reg[31:0] out_nextpc;
+
+reg[31:0] PC;
+reg tempstall;
+
+initial begin
+	PC = 32'h00000000;
+	tempstall = 1'b1;
+end
+
+always @(posedge clk) begin
+	if(tempstall == 1'b1) tempstall = 1'b0;
+	else if(stall == 1'b0 && flush == 1'b0) PC = PC+4;
+	out_nextpc = PC;
+end
+always @(negedge flush) begin
+	if(tempstall == 1'b0) PC = in_pc;
+	tempstall = 1'b1;
+end
+endmodule
+
+
 module IF_ID(clk, stall, flush, in_instruction, in_PC_4, 
 	out_instruction, out_PC_4);
 input clk, stall, flush;
@@ -8,35 +34,14 @@ output reg[31:0] out_instruction, out_PC_4;
 
 reg[31:0] temp_instruction, temp_PC_4;
 	
-reg first, stallfinished, flushed;
-
-initial begin
-	first = 1'b1;
-	stallfinished = 1'b0;
-	flushed = 1'b0;
-end
 always @(posedge clk) begin
 	if(stall == 1'b1) begin
 		out_instruction <= temp_instruction;
 		out_PC_4 <= temp_PC_4;
-	end
-	else if(flush == 1'b1) begin
+	end else if(flush == 1'b1) begin
 		out_instruction <= 32'h00000000;
 		out_PC_4 <= 32'h00000000;
-	end
-	else if(flushed == 1'b1) begin
-		out_instruction <= 32'h00000000;
-		out_PC_4 <= 32'h00000000;
-		stallfinished = 1'b0;
-		flushed = 1'b0;
-	end
-	else if(stallfinished == 1'b1) begin
-		out_instruction <= temp_instruction;
-		out_PC_4 <= temp_PC_4;		
-		stallfinished = 1'b0;
-		flushed = 1'b0;
-	end
-	else begin
+	end else begin
 		out_instruction <= in_instruction;
 		out_PC_4 <= in_PC_4;
 	end
@@ -45,17 +50,15 @@ always @(posedge stall) begin
 	temp_instruction <= out_instruction;
 	temp_PC_4 <= out_PC_4;
 end
-always @(negedge stall) stallfinished = 1'b1;
-always @(negedge flush) flushed = 1'b1;
 endmodule
 
 
-module ID_EX(clk, stall, flush, 
+module ID_EX(clk, flush, 
 	in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, in_link, 
 	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, 
 	out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, out_link, 
 	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
-input clk, stall, flush;
+input clk, flush;
 
 input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
 input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg, in_link;
@@ -69,33 +72,8 @@ output reg[3:0] out_aluctrl;
 output reg[2:0] out_branch;
 output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
 
-reg stallfinished;
-
-initial stallfinished = 1'b0;
 always @(posedge clk) begin
-	if(stall == 1'b1 || flush == 1'b1) begin
-		out_writereg_num <= 5'b00000;
-		out_readreg_num1 <= 5'b00000;
-		out_readreg_num2 <= 5'b00000;
-
-		out_regwrite <= 1'b0;
-		out_alusrc <= 1'b0;
-		out_aluctrl <= 4'b0000;
-		out_memread <= 1'b0;
-		out_memwrite <= 1'b0;
-		out_memtoreg <= 1'b0;
-		out_branch <= 3'b000;
-		out_jump <= 1'b0;
-		out_jumpreg <= 1'b0;
-		out_link <= 1'b0;
-
-		out_readdata1 <= 32'h00000000;
-		out_readdata2 <= 32'h00000000;
-		out_extenddata <= 32'h00000000;
-		out_PC_4 <= 32'h00000000;
-		out_tempPCjump <= 32'h00000000;
-	end 
-	else if(stallfinished == 1'b1) begin
+	if(flush == 1'b1) begin
 		out_writereg_num <= 5'b00000;
 		out_readreg_num1 <= 5'b00000;
 		out_readreg_num2 <= 5'b00000;
@@ -116,10 +94,7 @@ always @(posedge clk) begin
 		out_extenddata <= 32'h00000000;
 		out_PC_4 <= 32'h00000000;
 		out_tempPCjump <= 32'h00000000;
-		
-		stallfinished = 1'b0;
-	end 
-	else begin
+	end else begin
 		out_writereg_num <= in_writereg_num;
 		out_readreg_num1 <= in_readreg_num1;
 		out_readreg_num2 <= in_readreg_num2;
@@ -142,15 +117,14 @@ always @(posedge clk) begin
 		out_tempPCjump <= in_tempPCjump;
 	end
 end
-always @(negedge stall or negedge flush) stallfinished = 1'b1;
 endmodule
 
 
-module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link, 
+module EX_MEM(clk, flush, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link, 
 	in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 
 	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link, 
 	out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
-input clk;
+input clk, flush;
 
 input[4:0] in_writereg_num;
 input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link;
@@ -160,6 +134,22 @@ output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, ou
 output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;
 
 always @(posedge clk) begin
+	if(flush == 1'b1) begin
+		out_writereg_num <= 5'b00000;
+		out_regwrite <= 1'b0;
+		out_memread <= 1'b0;
+		out_memwrite <= 1'b0;
+		out_memtoreg <= 1'b0;
+		out_branch <= 1'b0;
+		out_jump <= 1'b0;
+		out_link <= 1'b0;
+
+		out_aluresult <= 32'h00000000;
+		out_mem_writedata <= 32'h00000000;
+		out_PC_4 <= 32'h00000000;
+		out_PCjump <= 32'h00000000;
+		out_tempPCbranch <= 32'h00000000;
+	end else begin
 		out_writereg_num <= in_writereg_num;
 		out_regwrite <= in_regwrite;
 		out_memread <= in_memread;
@@ -174,25 +164,41 @@ always @(posedge clk) begin
 		out_PC_4 <= in_PC_4;
 		out_PCjump <= in_PCjump;
 		out_tempPCbranch <= in_tempPCbranch;
+	end
 end
 endmodule
 
 
-module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_link, in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch, 
-	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_link, out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch);
-input clk;
+module MEM_WB(clk, flush, in_writereg_num, in_regwrite, in_memtoreg, in_branch, in_jump, in_link, in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch, 
+	out_writereg_num, out_regwrite, out_memtoreg, out_branch, out_jump, out_link, out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch);
+input clk, flush;
 
 input[4:0] in_writereg_num;
-input in_regwrite, in_memtoreg, in_jump, in_link;
+input in_regwrite, in_memtoreg, in_branch, in_jump, in_link;
 input[31:0] in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch;
 output reg[4:0] out_writereg_num;
-output reg out_regwrite, out_memtoreg, out_jump, out_link;
+output reg out_regwrite, out_memtoreg, out_branch, out_jump, out_link;
 output reg[31:0] out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch;
 
 always @(posedge clk) begin
+	if(flush == 1'b1) begin
+		out_writereg_num <= 5'b00000;
+		out_regwrite <= 1'b0;
+		out_memtoreg <= 1'b0;
+		out_branch <= 1'b0;
+		out_jump <= 1'b0;
+		out_link <= 1'b0;
+
+		out_aluresult <= 32'h00000000;
+		out_memreaddata <= 32'h00000000;
+		out_PC_4 <= 32'h00000000;
+		out_PCjump <= 32'h00000000;
+		out_PCbranch <= 32'h00000000;
+	end else begin
 		out_writereg_num <= in_writereg_num;
 		out_regwrite <= in_regwrite;
 		out_memtoreg <= in_memtoreg;
+		out_branch <= in_branch;
 		out_jump <= in_jump;
 		out_link <= in_link;
 
@@ -201,29 +207,7 @@ always @(posedge clk) begin
 		out_PC_4 <= in_PC_4;
 		out_PCjump <= in_PCjump;
 		out_PCbranch <= in_PCbranch;
+	end
 end
 endmodule
 
-/* Not Finished */
-module PCcounter(clk, stall, flush, in_pc, out_nextpc);
-input clk, stall, flush;
-
-input[31:0] in_pc;
-output reg[31:0] out_nextpc;
-
-reg[31:0] PC;
-reg stallfinished;
-
-initial begin
-	PC = 32'h00000000;
-	stallfinished = 1'b1;
-end
-
-always @(posedge clk) begin
-	if(stallfinished == 1'b1) stallfinished = 1'b0;
-	else if(stall == 1'b0 && flush == 1'b0) PC = PC+4;
-	out_nextpc = PC;
-end
-always @(negedge stall or negedge flush) stallfinished = 1'b1;
-always @(posedge flush) PC = in_pc;
-endmodule

@@ -4,6 +4,14 @@ output reg clk;
 
 initial clk = 0;
 always #50 clk = ~clk;
+endmodule
+
+
+module Clock_pipeline(clk);
 
+output reg clk;
+
+initial clk = 0;
+always #11 clk = ~clk;
 endmodule
 

@@ -9,7 +9,7 @@ z2
 cModel Technology
 dC:/Modeltech_pe_edu_10.4a/examples
 vAdder
-Z0 !s110 1591983139
+Z0 !s110 1592304743
 !i10b 1
 !s100 LKl?GBS:oo[A[hLP0Qb^_1
 IlbJEP?2C3Ya>zhzD12^S]1
@@ -23,7 +23,7 @@ Z3 OP;L;10.4a;61
 r1
 !s85 0
 31
-Z4 !s108 1591983139.000000
+Z4 !s108 1592304743.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s101 -O0
@@ -31,13 +31,13 @@ Z4 !s108 1591983139.000000
 Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
 n@adder
 vALU
-R0
+Z6 !s110 1592304744
 !i10b 1
 !s100 z[hZ0^@Q34FnkzY3g0ioc2
 ImZ3]6XT73YVLGl?0_=9k33
 R1
 R2
-w1591452276
+w1592238365
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
 L0 1
@@ -53,35 +53,57 @@ R4
 R5
 n@a@l@u
 vClock
-R0
+R6
 !i10b 1
-!s100 OWQXV6kDYiT>ChTOoCFa]2
-IQ?l7WoBBid7ozVDn[8k:e3
+!s100 i65lY=7B8[4>bmAoJ2kDB2
+I0GMR?JQ97PaC17BI<HeS82
 R1
 R2
-w1591110854
-8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
-FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+Z7 w1592091089
+Z8 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
+Z9 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v
 L0 1
 R3
 r1
 !s85 0
 31
-R4
-!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
+Z10 !s108 1592304744.000000
+Z11 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
+Z12 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
 !s101 -O0
 !i113 1
 R5
 n@clock
+vClock_pipeline
+R6
+!i10b 1
+!s100 dPQB6MR4Y;CLL9a@O1o1B0
+I7@GBo9UQ711@mL4ZBf;@Z1
+R1
+R2
+R7
+R8
+R9
+L0 10
+R3
+r1
+!s85 0
+31
+R10
+R11
+R12
+!s101 -O0
+!i113 1
+R5
+n@clock_pipeline
 vControl
-Z6 !s110 1591983140
+R6
 !i10b 1
-!s100 NdQKEjPCPSHG<0<4CTgfz1
-Io?;>IIVLB=Zl;M_TSQZ9I2
+!s100 PKg@cjO2lUjfUI`iaE9QB2
+IX2Ii?h^g2a@DaCi9:L8BU1
 R1
 R2
-w1591975942
+w1592280009
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 L0 1
@@ -89,7 +111,7 @@ R3
 r1
 !s85 0
 31
-R4
+R10
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s101 -O0
@@ -103,7 +125,7 @@ R6
 I9=L>R4ccfGY8^T;U50LY?1
 R1
 R2
-w1591452257
+w1592238359
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v
 L0 1
@@ -111,7 +133,7 @@ R3
 r1
 !s85 0
 31
-Z7 !s108 1591983140.000000
+R10
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s101 -O0
@@ -119,89 +141,111 @@ Z7 !s108 1591983140.000000
 R5
 n@data@memory
 vEX_MEM
-Z8 !s110 1591983141
+Z13 !s110 1592304745
 !i10b 1
-!s100 ^^:n;T<R5`c:oReRzT=QT3
-IUKd^A=OJc08kD[zWg_`SA2
+!s100 k5Dc_]iZ1_]4AXAj8[5Y<1
+IeKKdJcFcgGh?YcYVb3j^N0
 R1
 R2
-Z9 w1591982553
-Z10 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-Z11 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-L0 149
+Z14 w1592266109
+Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+L0 123
 R3
 r1
 !s85 0
 31
-Z12 !s108 1591983141.000000
-Z13 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
-Z14 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z17 !s108 1592304745.000000
+Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
 !s101 -O0
 !i113 1
 R5
 n@e@x_@m@e@m
-vFlush
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 R6
 !i10b 1
-!s100 G^dZ>]FGe3h^`=G1P?aLA1
-IaJUhT0Va;e^W1QK:FQaQi2
+!s100 VKUz971>SQ`J8:URRMF9b0
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 R1
 R2
-Z15 w1591970913
-Z16 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
-Z17 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
-L0 26
+Z20 w1592303944
+Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+L0 2
 R3
 r1
 !s85 0
 31
-R7
-Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
-Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+R10
+Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
 !s101 -O0
 !i113 1
 R5
-n@flush
-vID_EX
-R8
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 !i10b 1
-!s100 ?MgFelQ<oVo:WHdjbIKo00
-ITSSi3aWmi:I7boRWd[i>H3
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 R1
 R2
-R9
-R10
-R11
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 R3
 r1
 !s85 0
 31
-R12
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 R13
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 R14
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 !i113 1
 R5
 n@i@d_@e@x
 vIF_ID
-R8
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 !i10b 1
-!s100 bEXSIWd8gnI`]GAUe_N>70
-IRmIoA42QB9iZ_NYh`X79>3
+!s100 bKKM:?Mi3;B]TOe]O7<e>3
+I[FaS1INGbXUlELb9411?G2
 R1
 R2
-R9
-R10
-R11
-L0 1
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 R3
 r1
 !s85 0
 31
-R12
-R13
-R14
+R17
+R18
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 !s101 -O0
 !i113 1
 R5
@@ -209,11 +253,11 @@ n@i@f_@i@d
 vInstructionMemory
 R6
 !i10b 1
-!s100 dUP:<mGld?9A^?GbR`HX41
-Ijoe6hdS43:Kg7S<nf[6_S3
+!s100 cSI5j20TebFBX<a8i4YC;1
+ILAL:4@oQ@4VF>=@T80I7=2
 R1
 R2
-w1591979413
+w1592295803
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 L0 1
@@ -221,7 +265,7 @@ R3
 r1
 !s85 0
 31
-R7
+R10
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s101 -O0
@@ -229,57 +273,79 @@ R7
 R5
 n@instruction@memory
 vMEM_WB
-R8
+R13
 !i10b 1
-!s100 9m=P24TTjNA?g>P@e6;[=2
-I3VBN<k:`mX_jIkFWMoi3a2
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 R1
 R2
-R9
-R10
-R11
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 R3
 r1
 !s85 0
 31
-R12
-R13
-R14
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 !s101 -O0
 !i113 1
 R5
 n@m@e@m_@w@b
 vMIPS_Pipeline
-R6
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 !i10b 1
-!s100 AkG9Fhg`zlP55C:McA:FM2
-IZRIYdAdZBSFN3o<CV_WgK0
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 R1
 R2
-w1591980998
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 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
-L0 2
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 R3
 r1
 !s85 0
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-R7
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 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s101 -O0
 !i113 1
 R5
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+!s101 -O0
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 vMIPS_SingleCycle
-R8
+R13
 !i10b 1
-!s100 ;_UzWlV_FikM_gED@zTjP2
-IQEAV;clN[65lKfZREk<=Q1
+!s100 gM[;Cl]DhJhX67JceN9VX0
+IEZ2gnb65W:EYTLgmRHR8f2
 R1
 R2
-w1591976493
+w1592102255
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 L0 1
@@ -287,7 +353,7 @@ R3
 r1
 !s85 0
 31
-R7
+R17
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s101 -O0
@@ -295,101 +361,123 @@ R7
 R5
 n@m@i@p@s_@single@cycle
 vMux32bit
-R8
+R13
 !i10b 1
 !s100 foJG^YU75_eND1Og;6Z>O1
 II3=gjhQD0_cn8mlDL]@bi1
 R1
 R2
-Z20 w1591452448
-Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
-Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Z25 w1591452448
+Z26 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Z27 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
 L0 15
 R3
 r1
 !s85 0
 31
-R12
-Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
-Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+R17
+Z28 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+Z29 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
 !s101 -O0
 !i113 1
 R5
 n@mux32bit
 vMux5bit
-R8
+R13
 !i10b 1
 !s100 oSd=[kHDJb<:G7LN4]6@e3
 IfiVXg_aB2GQG7?F@=HcEi0
 R1
 R2
+R25
+R26
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+L0 1
+R3
+r1
+!s85 0
+31
+R17
+R28
+R29
+!s101 -O0
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+R5
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+R6
+!i10b 1
+!s100 85b4ZkTg28cdHOcJHT1i<1
+Ii2ZN`=VNWde5:dd4gJ:@_3
+R1
+R2
 R20
 R21
 R22
-L0 1
+L0 124
 R3
 r1
 !s85 0
 31
-R12
+R10
 R23
 R24
 !s101 -O0
 !i113 1
 R5
-n@mux5bit
+n@mux_@forwarding
 vMuxBranchSignal
-R8
+R13
 !i10b 1
 !s100 H1RKS9h`Y6QFX88CRc<g[0
 IGJT?gXMKEEWH?G^lPN79V2
 R1
 R2
-R20
-R21
-R22
+R25
+R26
+R27
 L0 29
 R3
 r1
 !s85 0
 31
-R12
-R23
-R24
+R17
+R28
+R29
 !s101 -O0
 !i113 1
 R5
 n@mux@branch@signal
-vPCcounter
-R8
+vPCregister
+R13
 !i10b 1
-!s100 WeKa=V6mT9ZlU8@mTC`g42
-Il_T>dO3a82KCcjIcT0_8<0
+!s100 ZWKU[XiaKQUFo0lg:i>8J3
+IJN5hl<_id]kA5B6k4:9oE1
 R1
 R2
-R9
-R10
-R11
-L0 208
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 R3
 r1
 !s85 0
 31
-R12
-R13
-R14
+R17
+R18
+R19
 !s101 -O0
 !i113 1
 R5
-n@p@ccounter
+n@p@cregister
 vRegister
-R8
+R13
 !i10b 1
 !s100 bC`<7GaPg=bDaZoUR<ADa0
 I<aR5RJ2c1Qba>GdC]KZCd2
 R1
 R2
-w1591452599
+w1592238349
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
 L0 1
@@ -397,7 +485,7 @@ R3
 r1
 !s85 0
 31
-R12
+R17
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s101 -O0
@@ -405,7 +493,7 @@ R12
 R5
 n@register
 vShiftLeft2
-R8
+!s110 1592304746
 !i10b 1
 !s100 ]Zje9D[f?jFRnJBn`OeHc1
 I]0TYJ]_7?FkOoY=2GlT5=3
@@ -419,7 +507,7 @@ R3
 r1
 !s85 0
 31
-R12
+R17
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s101 -O0
@@ -448,25 +536,3 @@ R4
 !i113 1
 R5
 n@sign@extend
-vStall
-R6
-!i10b 1
-!s100 z^N=>UeP;k2mNYmKnG`WR2
-IOg[[<<GgT4k[<hhzADXMC3
-R1
-R2
-R15
-R16
-R17
-L0 2
-R3
-r1
-!s85 0
-31
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-R18
-R19
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-!i113 1
-R5
-n@stall