arm-cmse-secure.c
2.02 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
// RUN: %clang -mlittle-endian -mcmse -target thumbv8m.base-eabi -emit-llvm -S -o - %s | FileCheck %s
// RUN: %clang -mbig-endian -mcmse -target thumbv8m.base-eabi -emit-llvm -S -o - %s | FileCheck %s
#include <arm_cmse.h>
unsigned test_cmse_primitives(void *p) {
// CHECK: define {{.*}} i32 @test_cmse_primitives
cmse_address_info_t tt_val, ttt_val;
cmse_address_info_t tta_val, ttat_val;
unsigned sum;
tt_val = cmse_TT(p);
ttt_val = cmse_TTT(p);
tta_val = cmse_TTA(p);
ttat_val = cmse_TTAT(p);
// CHECK: call i32 @llvm.arm.cmse.tt
// CHECK: call i32 @llvm.arm.cmse.ttt
// CHECK: call i32 @llvm.arm.cmse.tta
// CHECK: call i32 @llvm.arm.cmse.ttat
sum = tt_val.value;
sum += ttt_val.value;
sum += tta_val.value;
sum += ttat_val.value;
sum += tt_val.flags.mpu_region;
sum += tt_val.flags.sau_region;
sum += tt_val.flags.mpu_region_valid;
sum += tt_val.flags.sau_region_valid;
sum += tt_val.flags.read_ok;
sum += tt_val.flags.readwrite_ok;
sum += tt_val.flags.nonsecure_read_ok;
sum += tt_val.flags.nonsecure_readwrite_ok;
sum += tt_val.flags.secure;
sum += tt_val.flags.idau_region_valid;
sum += tt_val.flags.idau_region;
return sum;
}
void *test_address_range(void *p) {
// CHECK: define {{.*}} i8* @test_address_range
return cmse_check_address_range(p, 128, CMSE_MPU_UNPRIV
| CMSE_MPU_NONSECURE
| CMSE_MPU_READWRITE);
// CHECK: call i32 @llvm.arm.cmse.tt
// CHECK: call i32 @llvm.arm.cmse.ttt
// CHECK: call i32 @llvm.arm.cmse.tta
// CHECK: call i32 @llvm.arm.cmse.ttat
}
typedef struct {
int x, y, z;
} Point;
void *test_pointed_object(void *p) {
// CHECK: define {{.*}} i8* @test_pointed_object
Point *pt = (Point *)p;
cmse_check_pointed_object(pt, CMSE_NONSECURE
| CMSE_MPU_READ
| CMSE_AU_NONSECURE);
// CHECK: call i32 @llvm.arm.cmse.tt
// CHECK: call i32 @llvm.arm.cmse.ttt
// CHECK: call i32 @llvm.arm.cmse.tta
// CHECK: call i32 @llvm.arm.cmse.ttat
}